Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // Copyright 2008 Openmoko, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) // Copyright 2008 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) //	Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) //	http://armlinux.simtec.co.uk/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) // S3C64XX CPU PM support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/pm_domain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "map.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <mach/irqs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include "cpu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include "devs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include "pm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include "wakeup-mask.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include "regs-gpio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include "regs-clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include "gpio-samsung.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include "regs-gpio-memport-s3c64xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include "regs-modem-s3c64xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include "regs-sys-s3c64xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include "regs-syscon-power-s3c64xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) struct s3c64xx_pm_domain {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	char *const name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	u32 ena;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	u32 pwr_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	struct generic_pm_domain pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) static int s3c64xx_pd_off(struct generic_pm_domain *domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	struct s3c64xx_pm_domain *pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	pd = container_of(domain, struct s3c64xx_pm_domain, pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	val = __raw_readl(S3C64XX_NORMAL_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	val &= ~(pd->ena);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	__raw_writel(val, S3C64XX_NORMAL_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static int s3c64xx_pd_on(struct generic_pm_domain *domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	struct s3c64xx_pm_domain *pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	long retry = 1000000L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	pd = container_of(domain, struct s3c64xx_pm_domain, pd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	val = __raw_readl(S3C64XX_NORMAL_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	val |= pd->ena;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	__raw_writel(val, S3C64XX_NORMAL_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	/* Not all domains provide power status readback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	if (pd->pwr_stat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 			cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 			if (__raw_readl(S3C64XX_BLK_PWR_STAT) & pd->pwr_stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		} while (retry--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		if (!retry) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 			pr_err("Failed to start domain %s\n", pd->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 			return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) static struct s3c64xx_pm_domain s3c64xx_pm_irom = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	.name = "IROM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	.ena = S3C64XX_NORMALCFG_IROM_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	.pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		.power_off = s3c64xx_pd_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		.power_on = s3c64xx_pd_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) static struct s3c64xx_pm_domain s3c64xx_pm_etm = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	.name = "ETM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	.ena = S3C64XX_NORMALCFG_DOMAIN_ETM_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	.pwr_stat = S3C64XX_BLKPWRSTAT_ETM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	.pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		.power_off = s3c64xx_pd_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		.power_on = s3c64xx_pd_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static struct s3c64xx_pm_domain s3c64xx_pm_s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	.name = "S",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	.ena = S3C64XX_NORMALCFG_DOMAIN_S_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	.pwr_stat = S3C64XX_BLKPWRSTAT_S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	.pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		.power_off = s3c64xx_pd_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		.power_on = s3c64xx_pd_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static struct s3c64xx_pm_domain s3c64xx_pm_f = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	.name = "F",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	.ena = S3C64XX_NORMALCFG_DOMAIN_F_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	.pwr_stat = S3C64XX_BLKPWRSTAT_F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	.pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		.power_off = s3c64xx_pd_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		.power_on = s3c64xx_pd_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static struct s3c64xx_pm_domain s3c64xx_pm_p = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	.name = "P",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	.ena = S3C64XX_NORMALCFG_DOMAIN_P_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	.pwr_stat = S3C64XX_BLKPWRSTAT_P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	.pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		.power_off = s3c64xx_pd_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		.power_on = s3c64xx_pd_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static struct s3c64xx_pm_domain s3c64xx_pm_i = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	.name = "I",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	.ena = S3C64XX_NORMALCFG_DOMAIN_I_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	.pwr_stat = S3C64XX_BLKPWRSTAT_I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	.pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		.power_off = s3c64xx_pd_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		.power_on = s3c64xx_pd_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static struct s3c64xx_pm_domain s3c64xx_pm_g = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	.name = "G",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	.ena = S3C64XX_NORMALCFG_DOMAIN_G_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	.pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		.power_off = s3c64xx_pd_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		.power_on = s3c64xx_pd_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static struct s3c64xx_pm_domain s3c64xx_pm_v = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	.name = "V",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	.ena = S3C64XX_NORMALCFG_DOMAIN_V_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	.pwr_stat = S3C64XX_BLKPWRSTAT_V,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	.pd = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		.power_off = s3c64xx_pd_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		.power_on = s3c64xx_pd_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static struct s3c64xx_pm_domain *s3c64xx_always_on_pm_domains[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	&s3c64xx_pm_irom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static struct s3c64xx_pm_domain *s3c64xx_pm_domains[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	&s3c64xx_pm_etm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	&s3c64xx_pm_g,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	&s3c64xx_pm_v,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	&s3c64xx_pm_i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	&s3c64xx_pm_p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	&s3c64xx_pm_s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	&s3c64xx_pm_f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) void s3c_pm_debug_smdkled(u32 set, u32 clear)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	for (i = 0; i < 4; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		if (clear & (1 << i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 			gpio_set_value(S3C64XX_GPN(12 + i), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		if (set & (1 << i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			gpio_set_value(S3C64XX_GPN(12 + i), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static struct sleep_save core_save[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	SAVE_ITEM(S3C64XX_MEM0DRVCON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	SAVE_ITEM(S3C64XX_MEM1DRVCON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static struct sleep_save misc_save[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	SAVE_ITEM(S3C64XX_AHB_CON0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	SAVE_ITEM(S3C64XX_AHB_CON1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	SAVE_ITEM(S3C64XX_AHB_CON2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	SAVE_ITEM(S3C64XX_SPCON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	SAVE_ITEM(S3C64XX_MEM0CONSTOP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	SAVE_ITEM(S3C64XX_MEM1CONSTOP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	SAVE_ITEM(S3C64XX_MEM0CONSLP0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	SAVE_ITEM(S3C64XX_MEM0CONSLP1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	SAVE_ITEM(S3C64XX_MEM1CONSLP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	SAVE_ITEM(S3C64XX_SDMA_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	SAVE_ITEM(S3C64XX_MODEM_MIFPCON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	SAVE_ITEM(S3C64XX_NORMAL_CFG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) void s3c_pm_configure_extint(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	__raw_writel(s3c_irqwake_eintmask, S3C64XX_EINT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) void s3c_pm_restore_core(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	__raw_writel(0, S3C64XX_EINT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	s3c_pm_debug_smdkled(1 << 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) void s3c_pm_save_core(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* since both s3c6400 and s3c6410 share the same sleep pm calls, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)  * put the per-cpu code in here until any new cpu comes along and changes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)  * this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static int s3c64xx_cpu_suspend(unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	unsigned long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	/* set our standby method to sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	tmp = __raw_readl(S3C64XX_PWR_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	tmp &= ~S3C64XX_PWRCFG_CFG_WFI_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	tmp |= S3C64XX_PWRCFG_CFG_WFI_SLEEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	__raw_writel(tmp, S3C64XX_PWR_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	/* clear any old wakeup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	__raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		     S3C64XX_WAKEUP_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	/* set the LED state to 0110 over sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	s3c_pm_debug_smdkled(3 << 1, 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	/* issue the standby signal into the pm unit. Note, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	 * issue a write-buffer drain just in case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	asm("b 1f\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	    ".align 5\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	    "1:\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	    "mcr p15, 0, %0, c7, c10, 5\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	    "mcr p15, 0, %0, c7, c10, 4\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	    "mcr p15, 0, %0, c7, c0, 4" :: "r" (tmp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	/* we should never get past here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	pr_info("Failed to suspend the system\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	return 1; /* Aborting suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* mapping of interrupts to parts of the wakeup mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static const struct samsung_wakeup_mask wake_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	{ .irq = IRQ_RTC_ALARM,	.bit = S3C64XX_PWRCFG_RTC_ALARM_DISABLE, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	{ .irq = IRQ_RTC_TIC,	.bit = S3C64XX_PWRCFG_RTC_TICK_DISABLE, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	{ .irq = IRQ_PENDN,	.bit = S3C64XX_PWRCFG_TS_DISABLE, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	{ .irq = IRQ_HSMMC0,	.bit = S3C64XX_PWRCFG_MMC0_DISABLE, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	{ .irq = IRQ_HSMMC1,	.bit = S3C64XX_PWRCFG_MMC1_DISABLE, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	{ .irq = IRQ_HSMMC2,	.bit = S3C64XX_PWRCFG_MMC2_DISABLE, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	{ .irq = NO_WAKEUP_IRQ,	.bit = S3C64XX_PWRCFG_BATF_DISABLE},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	{ .irq = NO_WAKEUP_IRQ,	.bit = S3C64XX_PWRCFG_MSM_DISABLE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	{ .irq = NO_WAKEUP_IRQ,	.bit = S3C64XX_PWRCFG_HSI_DISABLE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	{ .irq = NO_WAKEUP_IRQ,	.bit = S3C64XX_PWRCFG_MSM_DISABLE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static void s3c64xx_pm_prepare(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	samsung_sync_wakemask(S3C64XX_PWR_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 			      wake_irqs, ARRAY_SIZE(wake_irqs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	/* store address of resume. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	__raw_writel(__pa_symbol(s3c_cpu_resume), S3C64XX_INFORM0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	/* ensure previous wakeup state is cleared before sleeping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	__raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), S3C64XX_WAKEUP_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #ifdef CONFIG_SAMSUNG_PM_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) void s3c_pm_arch_update_uart(void __iomem *regs, struct pm_uart_save *save)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	u32 ucon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	u32 ucon_clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	u32 save_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	u32 new_ucon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	u32 delta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	if (!soc_is_s3c64xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	ucon = __raw_readl(regs + S3C2410_UCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	ucon_clk = ucon & S3C6400_UCON_CLKMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	sav_clk = save->ucon & S3C6400_UCON_CLKMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	/* S3C64XX UART blocks only support level interrupts, so ensure that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	 * when we restore unused UART blocks we force the level interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	 * settigs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	/* We have a constraint on changing the clock type of the UART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	 * between UCLKx and PCLK, so ensure that when we restore UCON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	 * that the CLK field is correctly modified if the bootloader
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	 * has changed anything.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	if (ucon_clk != save_clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		new_ucon = save->ucon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		delta = ucon_clk ^ save_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		/* change from UCLKx => wrong PCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		 * either UCLK can be tested for by a bit-test
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		 * with UCLK0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		if (ucon_clk & S3C6400_UCON_UCLK0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		    !(save_clk & S3C6400_UCON_UCLK0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		    delta & S3C6400_UCON_PCLK2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 			new_ucon &= ~S3C6400_UCON_UCLK0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		} else if (delta == S3C6400_UCON_PCLK2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 			/* as an precaution, don't change from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 			 * PCLK2 => PCLK or vice-versa */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 			new_ucon ^= S3C6400_UCON_PCLK2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 			  ucon, new_ucon, save->ucon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		save->ucon = new_ucon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) int __init s3c64xx_pm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	s3c_pm_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	for (i = 0; i < ARRAY_SIZE(s3c64xx_always_on_pm_domains); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		pm_genpd_init(&s3c64xx_always_on_pm_domains[i]->pd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 			      &pm_domain_always_on_gov, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	for (i = 0; i < ARRAY_SIZE(s3c64xx_pm_domains); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		pm_genpd_init(&s3c64xx_pm_domains[i]->pd, NULL, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #ifdef CONFIG_S3C_DEV_FB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	if (dev_get_platdata(&s3c_device_fb.dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		pm_genpd_add_device(&s3c64xx_pm_f.pd, &s3c_device_fb.dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static __init int s3c64xx_pm_initcall(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	if (!soc_is_s3c64xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	pm_cpu_prep = s3c64xx_pm_prepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	pm_cpu_sleep = s3c64xx_cpu_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	gpio_request(S3C64XX_GPN(12), "DEBUG_LED0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	gpio_request(S3C64XX_GPN(13), "DEBUG_LED1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	gpio_request(S3C64XX_GPN(14), "DEBUG_LED2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	gpio_request(S3C64XX_GPN(15), "DEBUG_LED3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	gpio_direction_output(S3C64XX_GPN(12), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	gpio_direction_output(S3C64XX_GPN(13), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	gpio_direction_output(S3C64XX_GPN(14), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	gpio_direction_output(S3C64XX_GPN(15), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) arch_initcall(s3c64xx_pm_initcall);