^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (c) 2004-2006 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // S3C24XX Power Manager (Suspend-To-RAM) support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) // See Documentation/arm/samsung-s3c24xx/suspend.rst for more information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) // Parts based on arch/arm/mach-pxa/pm.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) // Thanks to Dimitry Andric for debugging
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/serial_s3c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "regs-clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "regs-gpio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "regs-irq.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "gpio-samsung.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/mach/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "gpio-cfg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "pm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "regs-mem-s3c24xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PFX "s3c24xx-pm: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static struct sleep_save core_save[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* we restore the timings here, with the proviso that the board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * brings the system up in an slower, or equal frequency setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * to the original system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * if we cannot guarantee this, then things are going to go very
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * wrong here, as we modify the refresh and both pll settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) SAVE_ITEM(S3C2410_BWSCON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) SAVE_ITEM(S3C2410_BANKCON0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) SAVE_ITEM(S3C2410_BANKCON1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) SAVE_ITEM(S3C2410_BANKCON2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) SAVE_ITEM(S3C2410_BANKCON3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) SAVE_ITEM(S3C2410_BANKCON4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) SAVE_ITEM(S3C2410_BANKCON5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* s3c_pm_check_resume_pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * check to see if the pin is configured correctly for sleep mode, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * make any necessary adjustments if it is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned long irqstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned long pinstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) int irq = gpio_to_irq(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (irqoffs < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) irqstate = s3c_irqwake_intmask & (1L<<irqoffs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) irqstate = s3c_irqwake_eintmask & (1L<<irqoffs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) pinstate = s3c_gpio_getcfg(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (!irqstate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (pinstate == S3C2410_GPIO_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) S3C_PMDBG("Leaving IRQ %d (pin %d) as is\n", irq, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (pinstate == S3C2410_GPIO_IRQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) S3C_PMDBG("Disabling IRQ %d (pin %d)\n", irq, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) s3c_gpio_cfgpin(pin, S3C2410_GPIO_INPUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* s3c_pm_configure_extint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * configure all external interrupt pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) void s3c_pm_configure_extint(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* for each of the external interrupts (EINT0..EINT15) we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * need to check whether it is an external interrupt source,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * and then configure it as an input if it is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) for (pin = S3C2410_GPF(0); pin <= S3C2410_GPF(7); pin++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) s3c_pm_check_resume_pin(pin, pin - S3C2410_GPF(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) for (pin = S3C2410_GPG(0); pin <= S3C2410_GPG(7); pin++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) s3c_pm_check_resume_pin(pin, (pin - S3C2410_GPG(0))+8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) void s3c_pm_restore_core(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) void s3c_pm_save_core(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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