^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (c) 2006 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // S3C2410 (and compatible) Power Manager (Suspend-To-RAM) support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "regs-gpio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "gpio-samsung.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "gpio-cfg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "cpu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "pm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "h1940.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static void s3c2410_pm_prepare(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* ensure at least GSTATUS3 has the resume address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) __raw_writel(__pa_symbol(s3c_cpu_resume), S3C2410_GSTATUS3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) S3C_PMDBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) S3C_PMDBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) if (machine_is_h1940()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) void *base = phys_to_virt(H1940_SUSPEND_CHECK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned long ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned long calc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* generate check for the bootloader to check on resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) for (ptr = 0; ptr < 0x40000; ptr += 0x400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) calc += __raw_readl(base+ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* RX3715 and RX1950 use similar to H1940 code and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * same offsets for resume and checksum pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (machine_is_rx3715() || machine_is_rx1950()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) void *base = phys_to_virt(H1940_SUSPEND_CHECK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned long ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned long calc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* generate check for the bootloader to check on resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) for (ptr = 0; ptr < 0x40000; ptr += 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) calc += __raw_readl(base+ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (machine_is_aml_m5900()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) gpio_request_one(S3C2410_GPF(2), GPIOF_OUT_INIT_HIGH, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) gpio_free(S3C2410_GPF(2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (machine_is_rx1950()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* According to S3C2442 user's manual, page 7-17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * when the system is operating in NAND boot mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * the hardware pin configuration - EINT[23:21] –
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * must be set as input for starting up after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * wakeup from sleep mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) s3c_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_INPUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) s3c_gpio_cfgpin(S3C2410_GPG(14), S3C2410_GPIO_INPUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) s3c_gpio_cfgpin(S3C2410_GPG(15), S3C2410_GPIO_INPUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static void s3c2410_pm_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) unsigned long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* unset the return-from-sleep flag, to ensure reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) tmp = __raw_readl(S3C2410_GSTATUS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) tmp &= S3C2410_GSTATUS2_OFFRESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) __raw_writel(tmp, S3C2410_GSTATUS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (machine_is_aml_m5900()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) gpio_request_one(S3C2410_GPF(2), GPIOF_OUT_INIT_LOW, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) gpio_free(S3C2410_GPF(2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct syscore_ops s3c2410_pm_syscore_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .resume = s3c2410_pm_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int s3c2410_pm_add(struct device *dev, struct subsys_interface *sif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) pm_cpu_prep = s3c2410_pm_prepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) pm_cpu_sleep = s3c2410_cpu_suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #if defined(CONFIG_CPU_S3C2410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static struct subsys_interface s3c2410_pm_interface = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .name = "s3c2410_pm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .subsys = &s3c2410_subsys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .add_dev = s3c2410_pm_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* register ourselves */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int __init s3c2410_pm_drvinit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return subsys_interface_register(&s3c2410_pm_interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) arch_initcall(s3c2410_pm_drvinit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static struct subsys_interface s3c2410a_pm_interface = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .name = "s3c2410a_pm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .subsys = &s3c2410a_subsys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .add_dev = s3c2410_pm_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int __init s3c2410a_pm_drvinit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return subsys_interface_register(&s3c2410a_pm_interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) arch_initcall(s3c2410a_pm_drvinit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #if defined(CONFIG_CPU_S3C2440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static struct subsys_interface s3c2440_pm_interface = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .name = "s3c2440_pm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .subsys = &s3c2440_subsys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .add_dev = s3c2410_pm_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static int __init s3c2440_pm_drvinit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return subsys_interface_register(&s3c2440_pm_interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) arch_initcall(s3c2440_pm_drvinit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #if defined(CONFIG_CPU_S3C2442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static struct subsys_interface s3c2442_pm_interface = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .name = "s3c2442_pm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .subsys = &s3c2442_subsys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .add_dev = s3c2410_pm_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static int __init s3c2442_pm_drvinit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return subsys_interface_register(&s3c2442_pm_interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) arch_initcall(s3c2442_pm_drvinit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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