^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (c) 2006-2007 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // http://armlinux.simtec.co.uk/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Vincent Sanders <vince@arm.linux.org.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) // S3C2440/S3C2442 CPU PLL tables (12MHz Crystal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/soc/samsung/s3c-cpufreq-core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/soc/samsung/s3c-pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* This array should be sorted in ascending order of the frequencies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static struct cpufreq_frequency_table s3c2440_plls_12[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) { .frequency = 75000000, .driver_data = PLLVAL(0x75, 3, 3), }, /* FVco 600.000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) { .frequency = 80000000, .driver_data = PLLVAL(0x98, 4, 3), }, /* FVco 640.000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) { .frequency = 90000000, .driver_data = PLLVAL(0x70, 2, 3), }, /* FVco 720.000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) { .frequency = 100000000, .driver_data = PLLVAL(0x5c, 1, 3), }, /* FVco 800.000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) { .frequency = 110000000, .driver_data = PLLVAL(0x66, 1, 3), }, /* FVco 880.000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) { .frequency = 120000000, .driver_data = PLLVAL(0x70, 1, 3), }, /* FVco 960.000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) { .frequency = 150000000, .driver_data = PLLVAL(0x75, 3, 2), }, /* FVco 600.000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) { .frequency = 160000000, .driver_data = PLLVAL(0x98, 4, 2), }, /* FVco 640.000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) { .frequency = 170000000, .driver_data = PLLVAL(0x4d, 1, 2), }, /* FVco 680.000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) { .frequency = 180000000, .driver_data = PLLVAL(0x70, 2, 2), }, /* FVco 720.000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) { .frequency = 190000000, .driver_data = PLLVAL(0x57, 1, 2), }, /* FVco 760.000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) { .frequency = 200000000, .driver_data = PLLVAL(0x5c, 1, 2), }, /* FVco 800.000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) { .frequency = 210000000, .driver_data = PLLVAL(0x84, 2, 2), }, /* FVco 840.000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) { .frequency = 220000000, .driver_data = PLLVAL(0x66, 1, 2), }, /* FVco 880.000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) { .frequency = 230000000, .driver_data = PLLVAL(0x6b, 1, 2), }, /* FVco 920.000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) { .frequency = 240000000, .driver_data = PLLVAL(0x70, 1, 2), }, /* FVco 960.000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) { .frequency = 300000000, .driver_data = PLLVAL(0x75, 3, 1), }, /* FVco 600.000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) { .frequency = 310000000, .driver_data = PLLVAL(0x93, 4, 1), }, /* FVco 620.000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) { .frequency = 320000000, .driver_data = PLLVAL(0x98, 4, 1), }, /* FVco 640.000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) { .frequency = 330000000, .driver_data = PLLVAL(0x66, 2, 1), }, /* FVco 660.000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) { .frequency = 340000000, .driver_data = PLLVAL(0x4d, 1, 1), }, /* FVco 680.000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) { .frequency = 350000000, .driver_data = PLLVAL(0xa7, 4, 1), }, /* FVco 700.000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { .frequency = 360000000, .driver_data = PLLVAL(0x70, 2, 1), }, /* FVco 720.000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { .frequency = 370000000, .driver_data = PLLVAL(0xb1, 4, 1), }, /* FVco 740.000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) { .frequency = 380000000, .driver_data = PLLVAL(0x57, 1, 1), }, /* FVco 760.000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { .frequency = 390000000, .driver_data = PLLVAL(0x7a, 2, 1), }, /* FVco 780.000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { .frequency = 400000000, .driver_data = PLLVAL(0x5c, 1, 1), }, /* FVco 800.000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static int s3c2440_plls12_add(struct device *dev, struct subsys_interface *sif)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct clk *xtal_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned long xtal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) xtal_clk = clk_get(NULL, "xtal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (IS_ERR(xtal_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return PTR_ERR(xtal_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) xtal = clk_get_rate(xtal_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) clk_put(xtal_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (xtal == 12000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) printk(KERN_INFO "Using PLL table for 12MHz crystal\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return s3c_plltab_register(s3c2440_plls_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ARRAY_SIZE(s3c2440_plls_12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static struct subsys_interface s3c2440_plls12_interface = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .name = "s3c2440_plls12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .subsys = &s3c2440_subsys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .add_dev = s3c2440_plls12_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static int __init s3c2440_pll_12mhz(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return subsys_interface_register(&s3c2440_plls12_interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) arch_initcall(s3c2440_pll_12mhz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static struct subsys_interface s3c2442_plls12_interface = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .name = "s3c2442_plls12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .subsys = &s3c2442_subsys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .add_dev = s3c2440_plls12_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static int __init s3c2442_pll_12mhz(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return subsys_interface_register(&s3c2442_plls12_interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) arch_initcall(s3c2442_pll_12mhz);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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