Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // Samsung's S3C64XX generic DMA support using amba-pl08x driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) // Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/amba/bus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/amba/pl080.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/amba/pl08x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include "cpu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <mach/irqs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "map.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "regs-sys-s3c64xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) static int pl08x_get_xfer_signal(const struct pl08x_channel_data *cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	return cd->min_signal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) static void pl08x_put_xfer_signal(const struct pl08x_channel_data *cd, int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * DMA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) static struct pl08x_channel_data s3c64xx_dma0_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 		.bus_id = "uart0_tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 		.min_signal = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		.max_signal = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		.periph_buses = PL08X_AHB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		.bus_id = "uart0_rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		.min_signal = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		.max_signal = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		.periph_buses = PL08X_AHB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		.bus_id = "uart1_tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		.min_signal = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		.max_signal = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		.periph_buses = PL08X_AHB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		.bus_id = "uart1_rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		.min_signal = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		.max_signal = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		.periph_buses = PL08X_AHB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		.bus_id = "uart2_tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		.min_signal = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		.max_signal = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		.periph_buses = PL08X_AHB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		.bus_id = "uart2_rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		.min_signal = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		.max_signal = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		.periph_buses = PL08X_AHB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		.bus_id = "uart3_tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		.min_signal = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		.max_signal = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		.periph_buses = PL08X_AHB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		.bus_id = "uart3_rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		.min_signal = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		.max_signal = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		.periph_buses = PL08X_AHB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		.bus_id = "pcm0_tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		.min_signal = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		.max_signal = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		.periph_buses = PL08X_AHB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		.bus_id = "pcm0_rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		.min_signal = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		.max_signal = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		.periph_buses = PL08X_AHB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		.bus_id = "i2s0_tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		.min_signal = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		.max_signal = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		.periph_buses = PL08X_AHB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		.bus_id = "i2s0_rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		.min_signal = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		.max_signal = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		.periph_buses = PL08X_AHB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		.bus_id = "spi0_tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		.min_signal = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		.max_signal = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		.periph_buses = PL08X_AHB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		.bus_id = "spi0_rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		.min_signal = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		.max_signal = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		.periph_buses = PL08X_AHB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		.bus_id = "i2s2_tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		.min_signal = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		.max_signal = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		.periph_buses = PL08X_AHB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		.bus_id = "i2s2_rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		.min_signal = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		.max_signal = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		.periph_buses = PL08X_AHB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static const struct dma_slave_map s3c64xx_dma0_slave_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	{ "s3c6400-uart.0", "tx", &s3c64xx_dma0_info[0] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	{ "s3c6400-uart.0", "rx", &s3c64xx_dma0_info[1] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	{ "s3c6400-uart.1", "tx", &s3c64xx_dma0_info[2] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	{ "s3c6400-uart.1", "rx", &s3c64xx_dma0_info[3] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	{ "s3c6400-uart.2", "tx", &s3c64xx_dma0_info[4] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	{ "s3c6400-uart.2", "rx", &s3c64xx_dma0_info[5] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	{ "s3c6400-uart.3", "tx", &s3c64xx_dma0_info[6] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	{ "s3c6400-uart.3", "rx", &s3c64xx_dma0_info[7] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	{ "samsung-pcm.0", "tx", &s3c64xx_dma0_info[8] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	{ "samsung-pcm.0", "rx", &s3c64xx_dma0_info[9] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	{ "samsung-i2s.0", "tx", &s3c64xx_dma0_info[10] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	{ "samsung-i2s.0", "rx", &s3c64xx_dma0_info[11] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	{ "s3c6410-spi.0", "tx", &s3c64xx_dma0_info[12] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	{ "s3c6410-spi.0", "rx", &s3c64xx_dma0_info[13] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	{ "samsung-i2s.2", "tx", &s3c64xx_dma0_info[14] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	{ "samsung-i2s.2", "rx", &s3c64xx_dma0_info[15] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct pl08x_platform_data s3c64xx_dma0_plat_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	.memcpy_burst_size = PL08X_BURST_SZ_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	.memcpy_bus_width = PL08X_BUS_WIDTH_32_BITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	.memcpy_prot_buff = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	.memcpy_prot_cache = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	.lli_buses = PL08X_AHB1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	.mem_buses = PL08X_AHB1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	.get_xfer_signal = pl08x_get_xfer_signal,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	.put_xfer_signal = pl08x_put_xfer_signal,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	.slave_channels = s3c64xx_dma0_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	.num_slave_channels = ARRAY_SIZE(s3c64xx_dma0_info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	.slave_map = s3c64xx_dma0_slave_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	.slave_map_len = ARRAY_SIZE(s3c64xx_dma0_slave_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static AMBA_AHB_DEVICE(s3c64xx_dma0, "dma-pl080s.0", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			0x75000000, {IRQ_DMA0}, &s3c64xx_dma0_plat_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)  * DMA1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static struct pl08x_channel_data s3c64xx_dma1_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		.bus_id = "pcm1_tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		.min_signal = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		.max_signal = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		.periph_buses = PL08X_AHB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		.bus_id = "pcm1_rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		.min_signal = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		.max_signal = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		.periph_buses = PL08X_AHB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		.bus_id = "i2s1_tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		.min_signal = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		.max_signal = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		.periph_buses = PL08X_AHB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		.bus_id = "i2s1_rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		.min_signal = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		.max_signal = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		.periph_buses = PL08X_AHB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		.bus_id = "spi1_tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		.min_signal = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		.max_signal = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		.periph_buses = PL08X_AHB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		.bus_id = "spi1_rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		.min_signal = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		.max_signal = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		.periph_buses = PL08X_AHB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		.bus_id = "ac97_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		.min_signal = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		.max_signal = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		.periph_buses = PL08X_AHB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		.bus_id = "ac97_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		.min_signal = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		.max_signal = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		.periph_buses = PL08X_AHB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		.bus_id = "ac97_mic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		.min_signal = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		.max_signal = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		.periph_buses = PL08X_AHB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		.bus_id = "pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		.min_signal = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		.max_signal = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		.periph_buses = PL08X_AHB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		.bus_id = "irda",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		.min_signal = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		.max_signal = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		.periph_buses = PL08X_AHB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		.bus_id = "external",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		.min_signal = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		.max_signal = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		.periph_buses = PL08X_AHB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static const struct dma_slave_map s3c64xx_dma1_slave_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	{ "samsung-pcm.1", "tx", &s3c64xx_dma1_info[0] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	{ "samsung-pcm.1", "rx", &s3c64xx_dma1_info[1] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	{ "samsung-i2s.1", "tx", &s3c64xx_dma1_info[2] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	{ "samsung-i2s.1", "rx", &s3c64xx_dma1_info[3] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	{ "s3c6410-spi.1", "tx", &s3c64xx_dma1_info[4] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	{ "s3c6410-spi.1", "rx", &s3c64xx_dma1_info[5] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct pl08x_platform_data s3c64xx_dma1_plat_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	.memcpy_burst_size = PL08X_BURST_SZ_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	.memcpy_bus_width = PL08X_BUS_WIDTH_32_BITS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	.memcpy_prot_buff = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	.memcpy_prot_cache = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	.lli_buses = PL08X_AHB1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	.mem_buses = PL08X_AHB1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	.get_xfer_signal = pl08x_get_xfer_signal,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	.put_xfer_signal = pl08x_put_xfer_signal,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	.slave_channels = s3c64xx_dma1_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	.num_slave_channels = ARRAY_SIZE(s3c64xx_dma1_info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	.slave_map = s3c64xx_dma1_slave_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	.slave_map_len = ARRAY_SIZE(s3c64xx_dma1_slave_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static AMBA_AHB_DEVICE(s3c64xx_dma1, "dma-pl080s.1", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 			0x75100000, {IRQ_DMA1}, &s3c64xx_dma1_plat_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static int __init s3c64xx_pl080_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	if (!soc_is_s3c64xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	/* Set all DMA configuration to be DMA, not SDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	writel(0xffffff, S3C64XX_SDMA_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	if (of_have_populated_dt())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	amba_device_register(&s3c64xx_dma0_device, &iomem_resource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	amba_device_register(&s3c64xx_dma1_device, &iomem_resource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) arch_initcall(s3c64xx_pl080_init);