Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright 2005 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *	http://www.simtec.co.uk/products/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *	Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * OSIRIS - CPLD control constants
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * OSIRIS - Memory map definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef __MACH_S3C24XX_OSIRIS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define __MACH_S3C24XX_OSIRIS_H __FILE__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* CTRL0 - NAND WP control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define OSIRIS_CTRL0_NANDSEL		(0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define OSIRIS_CTRL0_BOOT_INT		(1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define OSIRIS_CTRL0_PCMCIA		(1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define OSIRIS_CTRL0_FIX8		(1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define OSIRIS_CTRL0_PCMCIA_nWAIT	(1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define OSIRIS_CTRL0_PCMCIA_nIOIS16	(1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define OSIRIS_CTRL1_FIX8		(1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define OSIRIS_ID_REVMASK		(0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* start peripherals off after the S3C2410 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define OSIRIS_IOADDR(x)	(S3C2410_ADDR((x) + 0x04000000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OSIRIS_PA_CPLD		(S3C2410_CS1 | (1<<26))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* we put the CPLD registers next, to get them out of the way */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OSIRIS_VA_CTRL0		OSIRIS_IOADDR(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OSIRIS_PA_CTRL0		(OSIRIS_PA_CPLD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OSIRIS_VA_CTRL1		OSIRIS_IOADDR(0x00100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OSIRIS_PA_CTRL1		(OSIRIS_PA_CPLD + (1<<23))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define OSIRIS_VA_CTRL2		OSIRIS_IOADDR(0x00200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OSIRIS_PA_CTRL2		(OSIRIS_PA_CPLD + (2<<23))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OSIRIS_VA_CTRL3		OSIRIS_IOADDR(0x00300000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OSIRIS_PA_CTRL3		(OSIRIS_PA_CPLD + (2<<23))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define OSIRIS_VA_IDREG		OSIRIS_IOADDR(0x00700000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OSIRIS_PA_IDREG		(OSIRIS_PA_CPLD + (7<<23))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #endif /* __MACH_S3C24XX_OSIRIS_H */