^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2008 Openmoko, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2008 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * http://armlinux.simtec.co.uk/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * S3C64XX - Memory map definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef __ASM_ARCH_MAP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define __ASM_ARCH_MAP_H __FILE__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <mach/map-base.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "map-s3c.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Post-mux Chip Select Regions Xm0CSn_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * These may be used by SROM, NAND or CF depending on settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define S3C64XX_PA_XM0CSN0 (0x10000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define S3C64XX_PA_XM0CSN1 (0x18000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define S3C64XX_PA_XM0CSN2 (0x20000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define S3C64XX_PA_XM0CSN3 (0x28000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define S3C64XX_PA_XM0CSN4 (0x30000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define S3C64XX_PA_XM0CSN5 (0x38000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* HSMMC units */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define S3C64XX_PA_HSMMC(x) (0x7C200000 + ((x) * 0x100000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define S3C64XX_PA_HSMMC0 S3C64XX_PA_HSMMC(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define S3C64XX_PA_HSMMC1 S3C64XX_PA_HSMMC(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define S3C64XX_PA_HSMMC2 S3C64XX_PA_HSMMC(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define S3C_PA_UART (0x7F005000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define S3C_PA_UART0 (S3C_PA_UART + 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define S3C_PA_UART1 (S3C_PA_UART + 0x400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define S3C_PA_UART2 (S3C_PA_UART + 0x800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define S3C_PA_UART3 (S3C_PA_UART + 0xC00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define S3C_UART_OFFSET (0x400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* See notes on UART VA mapping in debug-macro.S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define S3C_VA_UARTx(x) (S3C_VA_UART + (S3C_PA_UART & 0xfffff) + ((x) * S3C_UART_OFFSET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define S3C_VA_UART0 S3C_VA_UARTx(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define S3C_VA_UART1 S3C_VA_UARTx(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define S3C_VA_UART2 S3C_VA_UARTx(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define S3C_VA_UART3 S3C_VA_UARTx(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define S3C64XX_PA_SROM (0x70000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define S3C64XX_PA_ONENAND0 (0x70100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define S3C64XX_PA_ONENAND0_BUF (0x20000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define S3C64XX_SZ_ONENAND0_BUF (SZ_64M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* NAND and OneNAND1 controllers occupy the same register region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) (depending on SoC POP version) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define S3C64XX_PA_ONENAND1 (0x70200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define S3C64XX_PA_ONENAND1_BUF (0x28000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define S3C64XX_SZ_ONENAND1_BUF (SZ_64M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define S3C64XX_PA_NAND (0x70200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define S3C64XX_PA_FB (0x77100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define S3C64XX_PA_USB_HSOTG (0x7C000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define S3C64XX_PA_WATCHDOG (0x7E004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define S3C64XX_PA_RTC (0x7E005000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define S3C64XX_PA_KEYPAD (0x7E00A000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define S3C64XX_PA_ADC (0x7E00B000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define S3C64XX_PA_SYSCON (0x7E00F000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define S3C64XX_PA_AC97 (0x7F001000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define S3C64XX_PA_IIS0 (0x7F002000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define S3C64XX_PA_IIS1 (0x7F003000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define S3C64XX_PA_TIMER (0x7F006000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define S3C64XX_PA_IIC0 (0x7F004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define S3C64XX_PA_SPI0 (0x7F00B000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define S3C64XX_PA_SPI1 (0x7F00C000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define S3C64XX_PA_PCM0 (0x7F009000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define S3C64XX_PA_PCM1 (0x7F00A000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define S3C64XX_PA_IISV4 (0x7F00D000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define S3C64XX_PA_IIC1 (0x7F00F000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define S3C64XX_PA_GPIO (0x7F008000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define S3C64XX_SZ_GPIO SZ_4K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define S3C64XX_PA_SDRAM (0x50000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define S3C64XX_PA_CFCON (0x70300000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define S3C64XX_PA_VIC0 (0x71200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define S3C64XX_PA_VIC1 (0x71300000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define S3C64XX_PA_MODEM (0x74108000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define S3C64XX_PA_USBHOST (0x74300000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define S3C64XX_PA_USB_HSPHY (0x7C100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* compatibility defines. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define S3C_PA_TIMER S3C64XX_PA_TIMER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define S3C_PA_HSMMC0 S3C64XX_PA_HSMMC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define S3C_PA_HSMMC1 S3C64XX_PA_HSMMC1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define S3C_PA_HSMMC2 S3C64XX_PA_HSMMC2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define S3C_PA_IIC S3C64XX_PA_IIC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define S3C_PA_IIC1 S3C64XX_PA_IIC1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define S3C_PA_NAND S3C64XX_PA_NAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define S3C_PA_ONENAND S3C64XX_PA_ONENAND0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define S3C_PA_ONENAND_BUF S3C64XX_PA_ONENAND0_BUF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define S3C_SZ_ONENAND_BUF S3C64XX_SZ_ONENAND0_BUF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define S3C_PA_FB S3C64XX_PA_FB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define S3C_PA_USBHOST S3C64XX_PA_USBHOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define S3C_PA_RTC S3C64XX_PA_RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define S3C_PA_WDT S3C64XX_PA_WATCHDOG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define S3C_PA_SPI0 S3C64XX_PA_SPI0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define S3C_PA_SPI1 S3C64XX_PA_SPI1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SAMSUNG_PA_ADC S3C64XX_PA_ADC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SAMSUNG_PA_CFCON S3C64XX_PA_CFCON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SAMSUNG_PA_KEYPAD S3C64XX_PA_KEYPAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SAMSUNG_PA_TIMER S3C64XX_PA_TIMER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #endif /* __ASM_ARCH_6400_MAP_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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