^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2003 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * S3C2410 - Memory map definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __ASM_ARCH_MAP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __ASM_ARCH_MAP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <mach/map-base.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "map-s3c.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * interrupt controller is the first thing we put in, to make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * the assembly code for the irq detection easier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define S3C2410_PA_IRQ (0x4A000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define S3C24XX_SZ_IRQ SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* memory controller registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define S3C2410_PA_MEMCTRL (0x48000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define S3C24XX_SZ_MEMCTRL SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Timers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define S3C2410_PA_TIMER (0x51000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define S3C24XX_SZ_TIMER SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Clock and Power management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define S3C24XX_SZ_CLKPWR SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* USB Device port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define S3C2410_PA_USBDEV (0x52000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define S3C24XX_SZ_USBDEV SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define S3C2410_PA_WATCHDOG (0x53000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define S3C24XX_SZ_WATCHDOG SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* Standard size definitions for peripheral blocks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define S3C24XX_SZ_UART SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define S3C24XX_SZ_IIS SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define S3C24XX_SZ_ADC SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define S3C24XX_SZ_SPI SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define S3C24XX_SZ_SDI SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define S3C24XX_SZ_NAND SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define S3C24XX_SZ_GPIO SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* USB host controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define S3C2410_PA_USBHOST (0x49000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* S3C2416/S3C2443/S3C2450 High-Speed USB Gadget */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define S3C2416_PA_HSUDC (0x49800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define S3C2416_SZ_HSUDC (SZ_4K)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* DMA controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define S3C2410_PA_DMA (0x4B000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define S3C24XX_SZ_DMA SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Clock and Power management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define S3C2410_PA_CLKPWR (0x4C000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* LCD controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define S3C2410_PA_LCD (0x4D000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define S3C24XX_SZ_LCD SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* NAND flash controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define S3C2410_PA_NAND (0x4E000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* IIC hardware controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define S3C2410_PA_IIC (0x54000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* IIS controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define S3C2410_PA_IIS (0x55000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* RTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define S3C2410_PA_RTC (0x57000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define S3C24XX_SZ_RTC SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* ADC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define S3C2410_PA_ADC (0x58000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define S3C2410_PA_SPI (0x59000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define S3C2443_PA_SPI0 (0x52000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define S3C2443_PA_SPI1 S3C2410_PA_SPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define S3C2410_SPI1 (0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define S3C2412_SPI1 (0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* SDI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define S3C2410_PA_SDI (0x5A000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* CAMIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define S3C2440_PA_CAMIF (0x4F000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define S3C2440_SZ_CAMIF SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* AC97 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define S3C2440_PA_AC97 (0x5B000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define S3C2440_SZ_AC97 SZ_1M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* S3C2443/S3C2416 High-speed SD/MMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define S3C2443_PA_HSMMC (0x4A800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define S3C2416_PA_HSMMC0 (0x4AC00000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define S3C2443_PA_FB (0x4C800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* S3C2412 memory and IO controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define S3C2412_PA_SSMC (0x4F000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define S3C2412_PA_EBI (0x48800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* physical addresses of all the chip-select areas */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define S3C2410_CS0 (0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define S3C2410_CS1 (0x08000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define S3C2410_CS2 (0x10000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define S3C2410_CS3 (0x18000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define S3C2410_CS4 (0x20000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define S3C2410_CS5 (0x28000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define S3C2410_CS6 (0x30000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define S3C2410_CS7 (0x38000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define S3C2410_SDRAM_PA (S3C2410_CS6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Use a single interface for common resources between S3C24XX cpus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define S3C24XX_PA_IRQ S3C2410_PA_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define S3C24XX_PA_DMA S3C2410_PA_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define S3C24XX_PA_LCD S3C2410_PA_LCD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define S3C24XX_PA_TIMER S3C2410_PA_TIMER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define S3C24XX_PA_IIS S3C2410_PA_IIS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define S3C24XX_PA_RTC S3C2410_PA_RTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define S3C24XX_PA_ADC S3C2410_PA_ADC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define S3C24XX_PA_SPI S3C2410_PA_SPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define S3C24XX_PA_SPI1 (S3C2410_PA_SPI + S3C2410_SPI1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define S3C24XX_PA_SDI S3C2410_PA_SDI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define S3C24XX_PA_NAND S3C2410_PA_NAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define S3C_PA_FB S3C2443_PA_FB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define S3C_PA_IIC S3C2410_PA_IIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define S3C_PA_USBHOST S3C2410_PA_USBHOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define S3C_PA_HSMMC0 S3C2416_PA_HSMMC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define S3C_PA_HSMMC1 S3C2443_PA_HSMMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define S3C_PA_WDT S3C2410_PA_WATCHDOG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define S3C_PA_NAND S3C24XX_PA_NAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define S3C_PA_SPI0 S3C2443_PA_SPI0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define S3C_PA_SPI1 S3C2443_PA_SPI1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SAMSUNG_PA_TIMER S3C2410_PA_TIMER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #endif /* __ASM_ARCH_MAP_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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