^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright 2010 Darius Augulis <augulis.darius@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // Copyright 2008 Openmoko, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright 2008 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) // http://armlinux.simtec.co.uk/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/dm9000.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mtd/partitions.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/serial_s3c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "map.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "regs-gpio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "gpio-samsung.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <mach/irqs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/soc/samsung/s3c-adc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "cpu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "devs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include "fb.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/platform_data/mtd-nand-s3c2410.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/platform_data/touchscreen-s3c2410.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <video/platform_lcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <video/samsung_fimd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include "s3c64xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include "regs-modem-s3c64xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include "regs-srom-s3c64xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define UCON S3C2410_UCON_DEFAULT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static struct s3c2410_uartcfg real6410_uartcfgs[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .hwport = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .ucon = UCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .ulcon = ULCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .ufcon = UFCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .hwport = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .ucon = UCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .ulcon = ULCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .ufcon = UFCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .hwport = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .ucon = UCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .ulcon = ULCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .ufcon = UFCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) [3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .hwport = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .ucon = UCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .ulcon = ULCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .ufcon = UFCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* DM9000AEP 10/100 ethernet controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static struct resource real6410_dm9k_resource[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) [0] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) [1] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN1 + 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) [2] = DEFINE_RES_NAMED(S3C_EINT(7), 1, NULL, IORESOURCE_IRQ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) | IORESOURCE_IRQ_HIGHLEVEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static struct dm9000_plat_data real6410_dm9k_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static struct platform_device real6410_device_eth = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .name = "dm9000",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .num_resources = ARRAY_SIZE(real6410_dm9k_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .resource = real6410_dm9k_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .platform_data = &real6410_dm9k_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static struct s3c_fb_pd_win real6410_lcd_type0_fb_win = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .max_bpp = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .default_bpp = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .xres = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .yres = 272,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static struct fb_videomode real6410_lcd_type0_timing = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* 4.3" 480x272 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .left_margin = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .right_margin = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .upper_margin = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .lower_margin = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .hsync_len = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .vsync_len = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static struct s3c_fb_pd_win real6410_lcd_type1_fb_win = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .max_bpp = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .default_bpp = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .xres = 800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .yres = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static struct fb_videomode real6410_lcd_type1_timing = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* 7.0" 800x480 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .left_margin = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .right_margin = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .upper_margin = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .lower_margin = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .hsync_len = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .vsync_len = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .xres = 800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .yres = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static struct s3c_fb_platdata real6410_lcd_pdata[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .vtiming = &real6410_lcd_type0_timing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .win[0] = &real6410_lcd_type0_fb_win,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .vtiming = &real6410_lcd_type1_timing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .win[0] = &real6410_lcd_type1_fb_win,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static struct mtd_partition real6410_nand_part[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .name = "uboot",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .size = SZ_1M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .name = "kernel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .size = SZ_2M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .offset = SZ_1M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .name = "rootfs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .size = MTDPART_SIZ_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .offset = SZ_1M + SZ_2M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static struct s3c2410_nand_set real6410_nand_sets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .name = "nand",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .nr_chips = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .nr_partitions = ARRAY_SIZE(real6410_nand_part),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .partitions = real6410_nand_part,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static struct s3c2410_platform_nand real6410_nand_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .tacls = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .twrph0 = 55,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .twrph1 = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .nr_sets = ARRAY_SIZE(real6410_nand_sets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .sets = real6410_nand_sets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static struct platform_device *real6410_devices[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) &real6410_device_eth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) &s3c_device_hsmmc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) &s3c_device_hsmmc1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) &s3c_device_fb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) &s3c_device_nand,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) &s3c_device_adc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) &s3c_device_ohci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static void __init real6410_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) s3c64xx_init_io(NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) s3c24xx_init_clocks(12000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) s3c24xx_init_uarts(real6410_uartcfgs, ARRAY_SIZE(real6410_uartcfgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) s3c64xx_set_timer_source(S3C64XX_PWM3, S3C64XX_PWM4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* set the LCD type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) tmp = __raw_readl(S3C64XX_SPCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) __raw_writel(tmp, S3C64XX_SPCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* remove the LCD bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) tmp &= ~MIFPCON_LCD_BYPASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * real6410_features string
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * 0-9 LCD configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static char real6410_features_str[12] __initdata = "0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static int __init real6410_features_setup(char *str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) if (str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) strlcpy(real6410_features_str, str,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) sizeof(real6410_features_str));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) __setup("real6410=", real6410_features_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define FEATURE_SCREEN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct real6410_features_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) int done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int lcd_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static void real6410_parse_features(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct real6410_features_t *features,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) const char *features_str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) const char *fp = features_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) features->done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) features->lcd_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) while (*fp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) char f = *fp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) switch (f) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) case '0'...'9': /* tft screen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (features->done & FEATURE_SCREEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) printk(KERN_INFO "REAL6410: '%c' ignored, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) "screen type already set\n", f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) int li = f - '0';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (li >= ARRAY_SIZE(real6410_lcd_pdata))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) printk(KERN_INFO "REAL6410: '%c' out "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) "of range LCD mode\n", f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) features->lcd_index = li;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) features->done |= FEATURE_SCREEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static void __init real6410_machine_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u32 cs1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct real6410_features_t features = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) printk(KERN_INFO "REAL6410: Option string real6410=%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) real6410_features_str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* Parse the feature string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) real6410_parse_features(&features, real6410_features_str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) printk(KERN_INFO "REAL6410: selected LCD display is %dx%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) real6410_lcd_pdata[features.lcd_index].win[0]->xres,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) real6410_lcd_pdata[features.lcd_index].win[0]->yres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) s3c_fb_set_platdata(&real6410_lcd_pdata[features.lcd_index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) s3c_nand_set_platdata(&real6410_nand_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) s3c64xx_ts_set_platdata(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* configure nCS1 width to 16 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) cs1 = __raw_readl(S3C64XX_SROM_BW) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) (1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) (1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) S3C64XX_SROM_BW__NCS1__SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) __raw_writel(cs1, S3C64XX_SROM_BW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* set timing for nCS1 suitable for ethernet chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) __raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) (6 << S3C64XX_SROM_BCX__TACP__SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) (4 << S3C64XX_SROM_BCX__TCAH__SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) (1 << S3C64XX_SROM_BCX__TCOH__SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) (13 << S3C64XX_SROM_BCX__TACC__SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) (4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) (0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) gpio_request(S3C64XX_GPF(15), "LCD power");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) platform_add_devices(real6410_devices, ARRAY_SIZE(real6410_devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) MACHINE_START(REAL6410, "REAL6410")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* Maintainer: Darius Augulis <augulis.darius@gmail.com> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .atag_offset = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .nr_irqs = S3C64XX_NR_IRQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .init_irq = s3c6410_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .map_io = real6410_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .init_machine = real6410_machine_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .init_time = s3c64xx_timer_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) MACHINE_END
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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