^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (c) 2005-2008 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // http://armlinux.simtec.co.uk/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/serial_s3c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/mfd/tps65010.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/mach/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/platform_data/mtd-nand-s3c2410.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/platform_data/i2c-s3c2410.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/mtd/rawnand.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/mtd/nand_ecc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/mtd/partitions.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include "cpu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/soc/samsung/s3c-cpu-freq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include "devs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include "gpio-cfg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include "regs-gpio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include "gpio-samsung.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include "s3c24xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include "osiris.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include "regs-mem-s3c24xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* onboard perihperal map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static struct map_desc osiris_iodesc[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* ISA IO areas (may be over-written later) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .virtual = (u32)S3C24XX_VA_ISA_BYTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .pfn = __phys_to_pfn(S3C2410_CS5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .length = SZ_16M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .virtual = (u32)S3C24XX_VA_ISA_WORD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .pfn = __phys_to_pfn(S3C2410_CS5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .length = SZ_16M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* CPLD control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .virtual = (u32)OSIRIS_VA_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .pfn = __phys_to_pfn(OSIRIS_PA_CTRL0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .length = SZ_16K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .virtual = (u32)OSIRIS_VA_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .pfn = __phys_to_pfn(OSIRIS_PA_CTRL1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .length = SZ_16K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .virtual = (u32)OSIRIS_VA_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .pfn = __phys_to_pfn(OSIRIS_PA_CTRL2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .length = SZ_16K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .virtual = (u32)OSIRIS_VA_IDREG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .pfn = __phys_to_pfn(OSIRIS_PA_IDREG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .length = SZ_16K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .hwport = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .ucon = UCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .ulcon = ULCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .ufcon = UFCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .hwport = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .ucon = UCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .ulcon = ULCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .ufcon = UFCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .hwport = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .ucon = UCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .ulcon = ULCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .ufcon = UFCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* NAND Flash on Osiris board */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int external_map[] = { 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static int chip0_map[] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static int chip1_map[] = { 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static struct mtd_partition __initdata osiris_default_nand_part[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .name = "Boot Agent",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .size = SZ_16K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .name = "/boot",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .size = SZ_4M - SZ_16K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .offset = SZ_16K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .name = "user1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .offset = SZ_4M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .size = SZ_32M - SZ_4M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) [3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .name = "user2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .offset = SZ_32M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .size = MTDPART_SIZ_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static struct mtd_partition __initdata osiris_default_nand_part_large[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .name = "Boot Agent",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .size = SZ_128K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .name = "/boot",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .size = SZ_4M - SZ_128K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .offset = SZ_128K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .name = "user1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .offset = SZ_4M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .size = SZ_32M - SZ_4M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) [3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .name = "user2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .offset = SZ_32M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .size = MTDPART_SIZ_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* the Osiris has 3 selectable slots for nand-flash, the two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * on-board chip areas, as well as the external slot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * Note, there is no current hot-plug support for the External
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * socket.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static struct s3c2410_nand_set __initdata osiris_nand_sets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .name = "External",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .nr_chips = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .nr_map = external_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .options = NAND_SCAN_SILENT_NODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .partitions = osiris_default_nand_part,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .name = "chip0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .nr_chips = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .nr_map = chip0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .partitions = osiris_default_nand_part,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .name = "chip1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .nr_chips = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .nr_map = chip1_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .options = NAND_SCAN_SILENT_NODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .partitions = osiris_default_nand_part,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) slot = set->nr_map[slot] & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) slot, set, set->nr_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) tmp = __raw_readb(OSIRIS_VA_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) tmp &= ~OSIRIS_CTRL0_NANDSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) tmp |= slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) pr_debug("osiris_nand: ctrl0 now %02x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) __raw_writeb(tmp, OSIRIS_VA_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static struct s3c2410_platform_nand __initdata osiris_nand_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .tacls = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .twrph0 = 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .twrph1 = 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .nr_sets = ARRAY_SIZE(osiris_nand_sets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .sets = osiris_nand_sets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .select_chip = osiris_nand_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* PCMCIA control and configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static struct resource osiris_pcmcia_resource[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) [0] = DEFINE_RES_MEM(0x0f000000, SZ_1M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) [1] = DEFINE_RES_MEM(0x0c000000, SZ_1M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static struct platform_device osiris_pcmcia = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .name = "osiris-pcmcia",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .num_resources = ARRAY_SIZE(osiris_pcmcia_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .resource = osiris_pcmcia_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* Osiris power management device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static unsigned char pm_osiris_ctrl0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static int osiris_pm_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) pm_osiris_ctrl0 = __raw_readb(OSIRIS_VA_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) tmp = pm_osiris_ctrl0 & ~OSIRIS_CTRL0_NANDSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* ensure correct NAND slot is selected on resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if ((pm_osiris_ctrl0 & OSIRIS_CTRL0_BOOT_INT) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) tmp |= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) __raw_writeb(tmp, OSIRIS_VA_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* ensure that an nRESET is not generated on resume. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) gpio_request_one(S3C2410_GPA(21), GPIOF_OUT_INIT_HIGH, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) gpio_free(S3C2410_GPA(21));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static void osiris_pm_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (pm_osiris_ctrl0 & OSIRIS_CTRL0_FIX8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) __raw_writeb(OSIRIS_CTRL1_FIX8, OSIRIS_VA_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) __raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define osiris_pm_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define osiris_pm_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static struct syscore_ops osiris_pm_syscore_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .suspend = osiris_pm_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .resume = osiris_pm_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* Link for DVS driver to TPS65011 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static void osiris_tps_release(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* static device, do not need to release anything */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static struct platform_device osiris_tps_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .name = "osiris-dvs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .dev.release = osiris_tps_release,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static int osiris_tps_setup(struct i2c_client *client, void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) osiris_tps_device.dev.parent = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return platform_device_register(&osiris_tps_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static int osiris_tps_remove(struct i2c_client *client, void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) platform_device_unregister(&osiris_tps_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static struct tps65010_board osiris_tps_board = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .base = -1, /* GPIO can go anywhere at the moment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .setup = osiris_tps_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .teardown = osiris_tps_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* I2C devices fitted. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static struct i2c_board_info osiris_i2c_devs[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) I2C_BOARD_INFO("tps65011", 0x48),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .irq = IRQ_EINT20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .platform_data = &osiris_tps_board,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* Standard Osiris devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static struct platform_device *osiris_devices[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) &s3c2410_device_dclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) &s3c_device_i2c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) &s3c_device_wdt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) &s3c_device_nand,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) &osiris_pcmcia,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static struct s3c_cpufreq_board __initdata osiris_cpufreq = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .refresh = 7800, /* refresh period is 7.8usec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .auto_io = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .need_io = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static void __init osiris_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* check for the newer revision boards with large page nand */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if ((__raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK) >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) printk(KERN_INFO "OSIRIS-B detected (revision %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) __raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) osiris_nand_sets[0].partitions = osiris_default_nand_part_large;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* write-protect line to the NAND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) gpio_request_one(S3C2410_GPA(0), GPIOF_OUT_INIT_HIGH, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) gpio_free(S3C2410_GPA(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) __raw_writel(__raw_readl(S3C2410_BWSCON) | S3C2410_BWSCON_ST1 | S3C2410_BWSCON_ST2 | S3C2410_BWSCON_ST3 | S3C2410_BWSCON_ST4 | S3C2410_BWSCON_ST5, S3C2410_BWSCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static void __init osiris_init_time(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) s3c2440_init_clocks(12000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) s3c24xx_timer_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static void __init osiris_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) register_syscore_ops(&osiris_pm_syscore_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) s3c_i2c0_set_platdata(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) s3c_nand_set_platdata(&osiris_nand_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) s3c_cpufreq_setboard(&osiris_cpufreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) i2c_register_board_info(0, osiris_i2c_devs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ARRAY_SIZE(osiris_i2c_devs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) platform_add_devices(osiris_devices, ARRAY_SIZE(osiris_devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) MACHINE_START(OSIRIS, "Simtec-OSIRIS")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .atag_offset = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .map_io = osiris_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .init_irq = s3c2440_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .init_machine = osiris_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .init_time = osiris_init_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) MACHINE_END
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags