Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // Copyright 2010 Darius Augulis <augulis.darius@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) // Copyright 2008 Openmoko, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) // Copyright 2008 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) //	Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) //	http://armlinux.simtec.co.uk/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/dm9000.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/mtd/partitions.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/serial_s3c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include "map.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include "regs-gpio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include "gpio-samsung.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <linux/soc/samsung/s3c-adc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include "cpu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include "devs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include "fb.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #include <linux/platform_data/mtd-nand-s3c2410.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #include <linux/platform_data/mmc-sdhci-s3c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #include "sdhci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #include <linux/platform_data/touchscreen-s3c2410.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #include <mach/irqs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #include <video/platform_lcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #include <video/samsung_fimd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #include "s3c64xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #include "regs-modem-s3c64xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #include "regs-srom-s3c64xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define UCON S3C2410_UCON_DEFAULT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) static struct s3c2410_uartcfg mini6410_uartcfgs[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		.hwport	= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		.flags	= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		.ucon	= UCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		.ulcon	= ULCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		.ufcon	= UFCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		.hwport	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		.flags	= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		.ucon	= UCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		.ulcon	= ULCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		.ufcon	= UFCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		.hwport	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		.flags	= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		.ucon	= UCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		.ulcon	= ULCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		.ufcon	= UFCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		.hwport	= 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		.flags	= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		.ucon	= UCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		.ulcon	= ULCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		.ufcon	= UFCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) /* DM9000AEP 10/100 ethernet controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) static struct resource mini6410_dm9k_resource[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	[0] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	[1] = DEFINE_RES_MEM(S3C64XX_PA_XM0CSN1 + 4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	[2] = DEFINE_RES_NAMED(S3C_EINT(7), 1, NULL, IORESOURCE_IRQ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 					| IORESOURCE_IRQ_HIGHLEVEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) static struct dm9000_plat_data mini6410_dm9k_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	.flags		= (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) static struct platform_device mini6410_device_eth = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	.name		= "dm9000",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	.id		= -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	.num_resources	= ARRAY_SIZE(mini6410_dm9k_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	.resource	= mini6410_dm9k_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	.dev		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		.platform_data	= &mini6410_dm9k_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static struct mtd_partition mini6410_nand_part[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		.name	= "uboot",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		.size	= SZ_1M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		.offset	= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		.name	= "kernel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		.size	= SZ_2M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		.offset	= SZ_1M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		.name	= "rootfs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		.size	= MTDPART_SIZ_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		.offset	= SZ_1M + SZ_2M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static struct s3c2410_nand_set mini6410_nand_sets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		.name		= "nand",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		.nr_chips	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		.nr_partitions	= ARRAY_SIZE(mini6410_nand_part),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		.partitions	= mini6410_nand_part,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static struct s3c2410_platform_nand mini6410_nand_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	.tacls		= 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	.twrph0		= 55,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	.twrph1		= 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	.nr_sets	= ARRAY_SIZE(mini6410_nand_sets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	.sets		= mini6410_nand_sets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	.engine_type	= NAND_ECC_ENGINE_TYPE_SOFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static struct s3c_fb_pd_win mini6410_lcd_type0_fb_win = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	.max_bpp	= 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	.default_bpp	= 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	.xres		= 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	.yres		= 272,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static struct fb_videomode mini6410_lcd_type0_timing = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	/* 4.3" 480x272 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	.left_margin	= 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	.right_margin	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	.upper_margin	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	.lower_margin	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	.hsync_len	= 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	.vsync_len	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	.xres		= 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	.yres		= 272,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static struct s3c_fb_pd_win mini6410_lcd_type1_fb_win = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	.max_bpp	= 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	.default_bpp	= 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	.xres		= 800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	.yres		= 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static struct fb_videomode mini6410_lcd_type1_timing = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	/* 7.0" 800x480 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	.left_margin	= 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	.right_margin	= 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	.upper_margin	= 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	.lower_margin	= 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	.hsync_len	= 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	.vsync_len	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	.xres		= 800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	.yres		= 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static struct s3c_fb_platdata mini6410_lcd_pdata[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		.vtiming	= &mini6410_lcd_type0_timing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		.win[0]		= &mini6410_lcd_type0_fb_win,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		.setup_gpio	= s3c64xx_fb_gpio_setup_24bpp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		.vtiming	= &mini6410_lcd_type1_timing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		.win[0]		= &mini6410_lcd_type1_fb_win,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		.vidcon0	= VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static void mini6410_lcd_power_set(struct plat_lcd_data *pd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 				   unsigned int power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	if (power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		gpio_direction_output(S3C64XX_GPE(0), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		gpio_direction_output(S3C64XX_GPE(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static struct plat_lcd_data mini6410_lcd_power_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	.set_power	= mini6410_lcd_power_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static struct platform_device mini6410_lcd_powerdev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	.name			= "platform-lcd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	.dev.parent		= &s3c_device_fb.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	.dev.platform_data	= &mini6410_lcd_power_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static struct s3c_sdhci_platdata mini6410_hsmmc1_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	.max_width		= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	.cd_type		= S3C_SDHCI_CD_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	.ext_cd_gpio		= S3C64XX_GPN(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	.ext_cd_gpio_invert	= true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static struct platform_device *mini6410_devices[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	&mini6410_device_eth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	&s3c_device_hsmmc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	&s3c_device_hsmmc1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	&s3c_device_ohci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	&s3c_device_nand,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	&s3c_device_fb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	&mini6410_lcd_powerdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	&s3c_device_adc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static void __init mini6410_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	s3c64xx_init_io(NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	s3c64xx_set_xtal_freq(12000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	s3c24xx_init_uarts(mini6410_uartcfgs, ARRAY_SIZE(mini6410_uartcfgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	s3c64xx_set_timer_source(S3C64XX_PWM3, S3C64XX_PWM4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	/* set the LCD type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	tmp = __raw_readl(S3C64XX_SPCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	__raw_writel(tmp, S3C64XX_SPCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	/* remove the LCD bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	tmp &= ~MIFPCON_LCD_BYPASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	__raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)  * mini6410_features string
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)  * 0-9 LCD configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static char mini6410_features_str[12] __initdata = "0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static int __init mini6410_features_setup(char *str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	if (str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		strlcpy(mini6410_features_str, str,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 			sizeof(mini6410_features_str));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) __setup("mini6410=", mini6410_features_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define FEATURE_SCREEN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct mini6410_features_t {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	int done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	int lcd_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static void mini6410_parse_features(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		struct mini6410_features_t *features,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		const char *features_str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	const char *fp = features_str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	features->done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	features->lcd_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	while (*fp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		char f = *fp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		switch (f) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		case '0'...'9':	/* tft screen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 			if (features->done & FEATURE_SCREEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 				printk(KERN_INFO "MINI6410: '%c' ignored, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 					"screen type already set\n", f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 			} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 				int li = f - '0';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 				if (li >= ARRAY_SIZE(mini6410_lcd_pdata))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 					printk(KERN_INFO "MINI6410: '%c' out "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 						"of range LCD mode\n", f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 				else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 					features->lcd_index = li;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 				}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 			features->done |= FEATURE_SCREEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static void __init mini6410_machine_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	u32 cs1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	struct mini6410_features_t features = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	printk(KERN_INFO "MINI6410: Option string mini6410=%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 			mini6410_features_str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	/* Parse the feature string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	mini6410_parse_features(&features, mini6410_features_str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	printk(KERN_INFO "MINI6410: selected LCD display is %dx%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		mini6410_lcd_pdata[features.lcd_index].win[0]->xres,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		mini6410_lcd_pdata[features.lcd_index].win[0]->yres);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	s3c_nand_set_platdata(&mini6410_nand_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	s3c_fb_set_platdata(&mini6410_lcd_pdata[features.lcd_index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	s3c_sdhci1_set_platdata(&mini6410_hsmmc1_pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	s3c64xx_ts_set_platdata(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	/* configure nCS1 width to 16 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	cs1 = __raw_readl(S3C64XX_SROM_BW) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		(1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		(1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 			S3C64XX_SROM_BW__NCS1__SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	__raw_writel(cs1, S3C64XX_SROM_BW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	/* set timing for nCS1 suitable for ethernet chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	__raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		(6 << S3C64XX_SROM_BCX__TACP__SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		(4 << S3C64XX_SROM_BCX__TCAH__SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		(1 << S3C64XX_SROM_BCX__TCOH__SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		(13 << S3C64XX_SROM_BCX__TACC__SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		(4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		(0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	gpio_request(S3C64XX_GPF(15), "LCD power");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	gpio_request(S3C64XX_GPE(0), "LCD power");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	platform_add_devices(mini6410_devices, ARRAY_SIZE(mini6410_devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) MACHINE_START(MINI6410, "MINI6410")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	/* Maintainer: Darius Augulis <augulis.darius@gmail.com> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	.atag_offset	= 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	.nr_irqs	= S3C64XX_NR_IRQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	.init_irq	= s3c6410_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	.map_io		= mini6410_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	.init_machine	= mini6410_machine_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	.init_time	= s3c64xx_timer_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) MACHINE_END