^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright 2007 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // http://armlinux.simtec.co.uk/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/gpio/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/serial_s3c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <video/ili9320.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/spi/spi_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/mach/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/platform_data/mtd-nand-s3c2410.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/platform_data/i2c-s3c2410.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "hardware-s3c24xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include "regs-gpio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/platform_data/fb-s3c2410.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include "gpio-samsung.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/mtd/rawnand.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/mtd/nand_ecc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/mtd/partitions.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include "gpio-cfg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include "devs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include "cpu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include "pm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <linux/platform_data/usb-s3c2410_udc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include "s3c24xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include "s3c2412-power.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static struct map_desc jive_iodesc[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define UCON S3C2410_UCON_DEFAULT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static struct s3c2410_uartcfg jive_uartcfgs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .hwport = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .ucon = UCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .ulcon = ULCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .ufcon = UFCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .hwport = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .ucon = UCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .ulcon = ULCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .ufcon = UFCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .hwport = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .ucon = UCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .ulcon = ULCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .ufcon = UFCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Jive flash assignment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * 0x00000000-0x00028000 : uboot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * 0x00028000-0x0002c000 : uboot env
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * 0x0002c000-0x00030000 : spare
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * 0x00030000-0x00200000 : zimage A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * 0x00200000-0x01600000 : cramfs A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * 0x01600000-0x017d0000 : zimage B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * 0x017d0000-0x02bd0000 : cramfs B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * 0x02bd0000-0x03fd0000 : yaffs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static struct mtd_partition __initdata jive_imageA_nand_part[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Don't allow access to the bootloader from linux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .name = "uboot",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .size = (160 * SZ_1K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .mask_flags = MTD_WRITEABLE, /* force read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* spare */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .name = "spare",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .offset = (176 * SZ_1K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .size = (16 * SZ_1K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* booted images */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .name = "kernel (ro)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .offset = (192 * SZ_1K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .size = (SZ_2M) - (192 * SZ_1K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .mask_flags = MTD_WRITEABLE, /* force read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .name = "root (ro)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .offset = (SZ_2M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .size = (20 * SZ_1M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .mask_flags = MTD_WRITEABLE, /* force read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* yaffs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .name = "yaffs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .offset = (44 * SZ_1M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .size = (20 * SZ_1M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* bootloader environment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .name = "env",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .offset = (160 * SZ_1K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .size = (16 * SZ_1K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* upgrade images */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .name = "zimage",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .offset = (22 * SZ_1M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .size = (2 * SZ_1M) - (192 * SZ_1K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .name = "cramfs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .offset = (24 * SZ_1M) - (192*SZ_1K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .size = (20 * SZ_1M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static struct mtd_partition __initdata jive_imageB_nand_part[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* Don't allow access to the bootloader from linux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .name = "uboot",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .size = (160 * SZ_1K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .mask_flags = MTD_WRITEABLE, /* force read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* spare */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .name = "spare",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .offset = (176 * SZ_1K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .size = (16 * SZ_1K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* booted images */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .name = "kernel (ro)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .offset = (22 * SZ_1M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .size = (2 * SZ_1M) - (192 * SZ_1K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .mask_flags = MTD_WRITEABLE, /* force read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .name = "root (ro)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .offset = (24 * SZ_1M) - (192 * SZ_1K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .size = (20 * SZ_1M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .mask_flags = MTD_WRITEABLE, /* force read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* yaffs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .name = "yaffs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .offset = (44 * SZ_1M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .size = (20 * SZ_1M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* bootloader environment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .name = "env",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .offset = (160 * SZ_1K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .size = (16 * SZ_1K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* upgrade images */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .name = "zimage",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .offset = (192 * SZ_1K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .size = (2 * SZ_1M) - (192 * SZ_1K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .name = "cramfs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .offset = (2 * SZ_1M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .size = (20 * SZ_1M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static struct s3c2410_nand_set __initdata jive_nand_sets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .name = "flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .nr_chips = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .nr_partitions = ARRAY_SIZE(jive_imageA_nand_part),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .partitions = jive_imageA_nand_part,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static struct s3c2410_platform_nand __initdata jive_nand_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* set taken from osiris nand timings, possibly still conservative */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .tacls = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .twrph0 = 55,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .twrph1 = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .sets = jive_nand_sets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .nr_sets = ARRAY_SIZE(jive_nand_sets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static int __init jive_mtdset(char *options)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct s3c2410_nand_set *nand = &jive_nand_sets[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) unsigned long set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (options == NULL || options[0] == '\0')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (kstrtoul(options, 10, &set)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) printk(KERN_ERR "failed to parse mtdset=%s\n", options);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) switch (set) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) nand->nr_partitions = ARRAY_SIZE(jive_imageB_nand_part);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) nand->partitions = jive_imageB_nand_part;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* this is already setup in the nand info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) printk(KERN_ERR "Unknown mtd set %ld specified,"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) "using default.", set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* parse the mtdset= option given to the kernel command line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) __setup("mtdset=", jive_mtdset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* LCD timing and setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define LCD_XRES (240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define LCD_YRES (320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define LCD_LEFT_MARGIN (12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define LCD_RIGHT_MARGIN (12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define LCD_LOWER_MARGIN (12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define LCD_UPPER_MARGIN (12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define LCD_VSYNC (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define LCD_HSYNC (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define LCD_REFRESH (60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define LCD_HTOT (LCD_HSYNC + LCD_LEFT_MARGIN + LCD_XRES + LCD_RIGHT_MARGIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define LCD_VTOT (LCD_VSYNC + LCD_LOWER_MARGIN + LCD_YRES + LCD_UPPER_MARGIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static struct s3c2410fb_display jive_vgg2432a4_display[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .width = LCD_XRES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .height = LCD_YRES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .xres = LCD_XRES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .yres = LCD_YRES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .left_margin = LCD_LEFT_MARGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .right_margin = LCD_RIGHT_MARGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .upper_margin = LCD_UPPER_MARGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .lower_margin = LCD_LOWER_MARGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .hsync_len = LCD_HSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .vsync_len = LCD_VSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .pixclock = (1000000000000LL /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) (LCD_REFRESH * LCD_HTOT * LCD_VTOT)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .bpp = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .type = (S3C2410_LCDCON1_TFT16BPP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) S3C2410_LCDCON1_TFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .lcdcon5 = (S3C2410_LCDCON5_FRM565 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) S3C2410_LCDCON5_INVVLINE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) S3C2410_LCDCON5_INVVFRAME |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) S3C2410_LCDCON5_INVVDEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) S3C2410_LCDCON5_PWREN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* todo - put into gpio header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define S3C2410_GPCCON_MASK(x) (3 << ((x) * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define S3C2410_GPDCON_MASK(x) (3 << ((x) * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static struct s3c2410fb_mach_info jive_lcd_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .displays = jive_vgg2432a4_display,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .num_displays = ARRAY_SIZE(jive_vgg2432a4_display),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .default_display = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* Enable VD[2..7], VD[10..15], VD[18..23] and VCLK, syncs, VDEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * and disable the pull down resistors on pins we are using for LCD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .gpcup = (0xf << 1) | (0x3f << 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .gpcup_reg = S3C2410_GPCUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .gpccon = (S3C2410_GPC1_VCLK | S3C2410_GPC2_VLINE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) S3C2410_GPC3_VFRAME | S3C2410_GPC4_VM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) S3C2410_GPC10_VD2 | S3C2410_GPC11_VD3 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) S3C2410_GPC12_VD4 | S3C2410_GPC13_VD5 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) S3C2410_GPC14_VD6 | S3C2410_GPC15_VD7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .gpccon_mask = (S3C2410_GPCCON_MASK(1) | S3C2410_GPCCON_MASK(2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) S3C2410_GPCCON_MASK(3) | S3C2410_GPCCON_MASK(4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) S3C2410_GPCCON_MASK(10) | S3C2410_GPCCON_MASK(11) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) S3C2410_GPCCON_MASK(12) | S3C2410_GPCCON_MASK(13) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) S3C2410_GPCCON_MASK(14) | S3C2410_GPCCON_MASK(15)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .gpccon_reg = S3C2410_GPCCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .gpdup = (0x3f << 2) | (0x3f << 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .gpdup_reg = S3C2410_GPDUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .gpdcon = (S3C2410_GPD2_VD10 | S3C2410_GPD3_VD11 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) S3C2410_GPD4_VD12 | S3C2410_GPD5_VD13 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) S3C2410_GPD6_VD14 | S3C2410_GPD7_VD15 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) S3C2410_GPD10_VD18 | S3C2410_GPD11_VD19 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) S3C2410_GPD12_VD20 | S3C2410_GPD13_VD21 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) S3C2410_GPD14_VD22 | S3C2410_GPD15_VD23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .gpdcon_mask = (S3C2410_GPDCON_MASK(2) | S3C2410_GPDCON_MASK(3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) S3C2410_GPDCON_MASK(4) | S3C2410_GPDCON_MASK(5) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) S3C2410_GPDCON_MASK(6) | S3C2410_GPDCON_MASK(7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) S3C2410_GPDCON_MASK(10) | S3C2410_GPDCON_MASK(11)|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) S3C2410_GPDCON_MASK(12) | S3C2410_GPDCON_MASK(13)|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) S3C2410_GPDCON_MASK(14) | S3C2410_GPDCON_MASK(15)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .gpdcon_reg = S3C2410_GPDCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* ILI9320 support. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static void jive_lcm_reset(unsigned int set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) printk(KERN_DEBUG "%s(%d)\n", __func__, set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) gpio_set_value(S3C2410_GPG(13), set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #undef LCD_UPPER_MARGIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define LCD_UPPER_MARGIN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static struct ili9320_platdata jive_lcm_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .hsize = LCD_XRES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .vsize = LCD_YRES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .reset = jive_lcm_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .suspend = ILI9320_SUSPEND_DEEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .entry_mode = ILI9320_ENTRYMODE_ID(3) | ILI9320_ENTRYMODE_BGR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .display2 = (ILI9320_DISPLAY2_FP(LCD_UPPER_MARGIN) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ILI9320_DISPLAY2_BP(LCD_LOWER_MARGIN)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .display3 = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .display4 = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .rgb_if1 = (ILI9320_RGBIF1_RIM_RGB18 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ILI9320_RGBIF1_RM | ILI9320_RGBIF1_CLK_RGBIF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .rgb_if2 = ILI9320_RGBIF2_DPL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .interface2 = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .interface3 = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .interface4 = (ILI9320_INTERFACE4_RTNE(16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ILI9320_INTERFACE4_DIVE(1)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .interface5 = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .interface6 = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* LCD SPI support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static struct spi_gpio_platform_data jive_lcd_spi = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .num_chipselect = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static struct platform_device jive_device_lcdspi = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .name = "spi_gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .dev.platform_data = &jive_lcd_spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static struct gpiod_lookup_table jive_lcdspi_gpiod_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .dev_id = "spi_gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) GPIO_LOOKUP("GPIOG", 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) "sck", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) GPIO_LOOKUP("GPIOB", 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) "mosi", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) GPIO_LOOKUP("GPIOB", 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) "cs", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* WM8750 audio code SPI definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static struct spi_gpio_platform_data jive_wm8750_spi = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .num_chipselect = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static struct platform_device jive_device_wm8750 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .name = "spi_gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .id = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .dev.platform_data = &jive_wm8750_spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static struct gpiod_lookup_table jive_wm8750_gpiod_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .dev_id = "spi_gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) GPIO_LOOKUP("GPIOB", 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) "sck", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) GPIO_LOOKUP("GPIOB", 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) "mosi", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) GPIO_LOOKUP("GPIOH", 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) "cs", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* JIVE SPI devices. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static struct spi_board_info __initdata jive_spi_devs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .modalias = "VGG2432A4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .bus_num = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .chip_select = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .mode = SPI_MODE_3, /* CPOL=1, CPHA=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .max_speed_hz = 100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .platform_data = &jive_lcm_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .modalias = "WM8750",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .bus_num = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .chip_select = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .mode = SPI_MODE_0, /* CPOL=0, CPHA=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .max_speed_hz = 100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* I2C bus and device configuration. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static struct s3c2410_platform_i2c jive_i2c_cfg __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .frequency = 80 * 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .flags = S3C_IICFLG_FILTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .sda_delay = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static struct i2c_board_info jive_i2c_devs[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) I2C_BOARD_INFO("lis302dl", 0x1c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .irq = IRQ_EINT14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /* The platform devices being used. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static struct platform_device *jive_devices[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) &s3c_device_ohci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) &s3c_device_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) &s3c_device_wdt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) &s3c_device_i2c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) &s3c_device_lcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) &jive_device_lcdspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) &jive_device_wm8750,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) &s3c_device_nand,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) &s3c_device_usbgadget,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) &s3c2412_device_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static struct s3c2410_udc_mach_info jive_udc_cfg __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .vbus_pin = S3C2410_GPG(1), /* detect is on GPG1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* Jive power management device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static int jive_pm_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* Write the magic value u-boot uses to check for resume into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * the INFORM0 register, and ensure INFORM1 is set to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * correct address to resume from. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) __raw_writel(0x2BED, S3C2412_INFORM0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) __raw_writel(__pa_symbol(s3c_cpu_resume), S3C2412_INFORM1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static void jive_pm_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) __raw_writel(0x0, S3C2412_INFORM0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define jive_pm_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define jive_pm_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static struct syscore_ops jive_pm_syscore_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .suspend = jive_pm_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .resume = jive_pm_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static void __init jive_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static void __init jive_init_time(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) s3c2412_init_clocks(12000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) s3c24xx_timer_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static void jive_power_off(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) printk(KERN_INFO "powering system down...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) gpio_request_one(S3C2410_GPC(5), GPIOF_OUT_INIT_HIGH, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) gpio_free(S3C2410_GPC(5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static void __init jive_machine_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /* register system core operations for managing low level suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) register_syscore_ops(&jive_pm_syscore_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /* write our sleep configurations for the IO. Pull down all unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * IO, ensure that we have turned off all peripherals we do not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * need, and configure the ones we do need. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* Port B sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) __raw_writel(S3C2412_SLPCON_IN(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) S3C2412_SLPCON_PULL(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) S3C2412_SLPCON_HIGH(2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) S3C2412_SLPCON_PULL(3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) S3C2412_SLPCON_PULL(4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) S3C2412_SLPCON_PULL(5) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) S3C2412_SLPCON_PULL(6) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) S3C2412_SLPCON_HIGH(7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) S3C2412_SLPCON_PULL(8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) S3C2412_SLPCON_PULL(9) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) S3C2412_SLPCON_PULL(10), S3C2412_GPBSLPCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /* Port C sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) __raw_writel(S3C2412_SLPCON_PULL(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) S3C2412_SLPCON_PULL(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) S3C2412_SLPCON_PULL(2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) S3C2412_SLPCON_PULL(3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) S3C2412_SLPCON_PULL(4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) S3C2412_SLPCON_PULL(5) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) S3C2412_SLPCON_LOW(6) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) S3C2412_SLPCON_PULL(6) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) S3C2412_SLPCON_PULL(7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) S3C2412_SLPCON_PULL(8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) S3C2412_SLPCON_PULL(9) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) S3C2412_SLPCON_PULL(10) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) S3C2412_SLPCON_PULL(11) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) S3C2412_SLPCON_PULL(12) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) S3C2412_SLPCON_PULL(13) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) S3C2412_SLPCON_PULL(14) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) S3C2412_SLPCON_PULL(15), S3C2412_GPCSLPCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /* Port D sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) __raw_writel(S3C2412_SLPCON_ALL_PULL, S3C2412_GPDSLPCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /* Port F sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) __raw_writel(S3C2412_SLPCON_LOW(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) S3C2412_SLPCON_LOW(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) S3C2412_SLPCON_LOW(2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) S3C2412_SLPCON_EINT(3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) S3C2412_SLPCON_EINT(4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) S3C2412_SLPCON_EINT(5) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) S3C2412_SLPCON_EINT(6) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) S3C2412_SLPCON_EINT(7), S3C2412_GPFSLPCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /* Port G sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) __raw_writel(S3C2412_SLPCON_IN(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) S3C2412_SLPCON_IN(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) S3C2412_SLPCON_IN(2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) S3C2412_SLPCON_IN(3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) S3C2412_SLPCON_IN(4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) S3C2412_SLPCON_IN(5) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) S3C2412_SLPCON_IN(6) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) S3C2412_SLPCON_IN(7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) S3C2412_SLPCON_PULL(8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) S3C2412_SLPCON_PULL(9) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) S3C2412_SLPCON_IN(10) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) S3C2412_SLPCON_PULL(11) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) S3C2412_SLPCON_PULL(12) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) S3C2412_SLPCON_PULL(13) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) S3C2412_SLPCON_IN(14) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) S3C2412_SLPCON_PULL(15), S3C2412_GPGSLPCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* Port H sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) __raw_writel(S3C2412_SLPCON_PULL(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) S3C2412_SLPCON_PULL(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) S3C2412_SLPCON_PULL(2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) S3C2412_SLPCON_PULL(3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) S3C2412_SLPCON_PULL(4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) S3C2412_SLPCON_PULL(5) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) S3C2412_SLPCON_PULL(6) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) S3C2412_SLPCON_IN(7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) S3C2412_SLPCON_IN(8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) S3C2412_SLPCON_PULL(9) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) S3C2412_SLPCON_IN(10), S3C2412_GPHSLPCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* initialise the power management now we've setup everything. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) s3c_pm_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /** TODO - check that this is after the cmdline option! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) s3c_nand_set_platdata(&jive_nand_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) gpio_request(S3C2410_GPG(13), "lcm reset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) gpio_direction_output(S3C2410_GPG(13), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) gpio_request_one(S3C2410_GPB(6), GPIOF_OUT_INIT_LOW, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) gpio_free(S3C2410_GPB(6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /* Turn off suspend on both USB ports, and switch the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * selectable USB port to USB device mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) S3C2410_MISCCR_USBSUSPND0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) S3C2410_MISCCR_USBSUSPND1, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) s3c24xx_udc_set_platdata(&jive_udc_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) s3c24xx_fb_set_platdata(&jive_lcd_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) spi_register_board_info(jive_spi_devs, ARRAY_SIZE(jive_spi_devs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) s3c_i2c0_set_platdata(&jive_i2c_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) i2c_register_board_info(0, jive_i2c_devs, ARRAY_SIZE(jive_i2c_devs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) pm_power_off = jive_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) gpiod_add_lookup_table(&jive_lcdspi_gpiod_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) gpiod_add_lookup_table(&jive_wm8750_gpiod_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) platform_add_devices(jive_devices, ARRAY_SIZE(jive_devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) MACHINE_START(JIVE, "JIVE")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .atag_offset = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .init_irq = s3c2412_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .map_io = jive_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .init_machine = jive_machine_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .init_time = jive_init_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) MACHINE_END
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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