^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Speyside modules for Cragganmore - board data probing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright 2011 Wolfson Microelectronics plc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Mark Brown <broonie@opensource.wolfsonmicro.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/gpio/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mfd/wm831x/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mfd/wm831x/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mfd/wm8994/pdata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mfd/arizona/pdata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <sound/wm0010.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <sound/wm2200.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <sound/wm5100.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <sound/wm8996.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <sound/wm8962.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <sound/wm9081.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/platform_data/spi-s3c64xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "cpu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <mach/irqs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "crag6410.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static struct s3c64xx_spi_csinfo wm0010_spi_csinfo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .line = S3C64XX_GPC(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static struct wm0010_pdata wm0010_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .gpio_reset = S3C64XX_GPN(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .reset_active_high = 1, /* Active high for Glenfarclas Rev 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static struct spi_board_info wm1253_devs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .modalias = "wm0010",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .max_speed_hz = 26 * 1000 * 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .bus_num = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .chip_select = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .mode = SPI_MODE_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .irq = S3C_EINT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .controller_data = &wm0010_spi_csinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .platform_data = &wm0010_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static struct spi_board_info balblair_devs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .modalias = "wm0010",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .max_speed_hz = 26 * 1000 * 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .bus_num = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .chip_select = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .mode = SPI_MODE_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .irq = S3C_EINT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .controller_data = &wm0010_spi_csinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .platform_data = &wm0010_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static struct wm5100_pdata wm5100_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .ldo_ena = S3C64XX_GPN(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .irq_flags = IRQF_TRIGGER_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .gpio_base = CODEC_GPIO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .in_mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) WM5100_IN_DIFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) WM5100_IN_DIFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) WM5100_IN_DIFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) WM5100_IN_SE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .hp_pol = CODEC_GPIO_BASE + 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .jack_modes = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { WM5100_MICDET_MICBIAS3, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { WM5100_MICDET_MICBIAS2, 1, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .gpio_defaults = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) 0x2, /* IRQ: CMOS output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) 0x3, /* CLKOUT: CMOS output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static struct wm8996_retune_mobile_config wm8996_retune[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .name = "Sub LPF",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .rate = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 0x6318, 0x6300, 0x1000, 0x0000, 0x0004, 0x2000, 0xF000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 0x0000, 0x0004, 0x2000, 0xF000, 0x0000, 0x0004, 0x2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 0xF000, 0x0000, 0x0004, 0x1000, 0x0800, 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .name = "Sub HPF",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .rate = 48000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 0x000A, 0x6300, 0x1000, 0x0000, 0x0004, 0x2000, 0xF000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 0x0000, 0x0004, 0x2000, 0xF000, 0x0000, 0x0004, 0x2000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 0xF000, 0x0000, 0x0004, 0x1000, 0x0800, 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static struct wm8996_pdata wm8996_pdata __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .ldo_ena = S3C64XX_GPN(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .gpio_base = CODEC_GPIO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .micdet_def = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .inl_mode = WM8996_DIFFERRENTIAL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .inr_mode = WM8996_DIFFERRENTIAL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .irq_flags = IRQF_TRIGGER_RISING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .gpio_default = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 0x8001, /* GPIO1 == ADCLRCLK1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 0x8001, /* GPIO2 == ADCLRCLK2, input due to CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 0x0141, /* GPIO3 == HP_SEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 0x0002, /* GPIO4 == IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 0x020e, /* GPIO5 == CLKOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .retune_mobile_cfgs = wm8996_retune,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .num_retune_mobile_cfgs = ARRAY_SIZE(wm8996_retune),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static struct wm8962_pdata wm8962_pdata __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .gpio_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) WM8962_GPIO_FN_OPCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) WM8962_GPIO_FN_DMICCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 0x8000 | WM8962_GPIO_FN_DMICDAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) WM8962_GPIO_FN_IRQ, /* Open drain mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .in4_dc_measure = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static struct wm9081_pdata wm9081_pdata __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .irq_high = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .irq_cmos = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static const struct i2c_board_info wm1254_devs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { I2C_BOARD_INFO("wm8996", 0x1a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .platform_data = &wm8996_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { I2C_BOARD_INFO("wm9081", 0x6c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .platform_data = &wm9081_pdata, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const struct i2c_board_info wm1255_devs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { I2C_BOARD_INFO("wm5100", 0x1a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .platform_data = &wm5100_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { I2C_BOARD_INFO("wm9081", 0x6c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .platform_data = &wm9081_pdata, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static const struct i2c_board_info wm1259_devs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { I2C_BOARD_INFO("wm8962", 0x1a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .platform_data = &wm8962_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static struct regulator_init_data wm8994_ldo1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .supply_regulator = "WALLVDD",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static struct regulator_init_data wm8994_ldo2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .supply_regulator = "WALLVDD",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static struct wm8994_pdata wm8994_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .gpio_base = CODEC_GPIO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .micb2_delay = 150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .gpio_defaults = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 0x3, /* IRQ out, active high, CMOS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .ldo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { .init_data = &wm8994_ldo1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { .init_data = &wm8994_ldo2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static const struct i2c_board_info wm1277_devs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { I2C_BOARD_INFO("wm8958", 0x1a), /* WM8958 is the superset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .platform_data = &wm8994_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .dev_name = "wm8958",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static struct gpiod_lookup_table wm8994_gpiod_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .dev_id = "i2c-wm8958", /* I2C device name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) GPIO_LOOKUP("GPION", 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) "wlf,ldo1ena", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) GPIO_LOOKUP("GPION", 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) "wlf,ldo2ena", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static struct arizona_pdata wm5102_reva_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .gpio_base = CODEC_GPIO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .irq_flags = IRQF_TRIGGER_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .micd_pol_gpio = CODEC_GPIO_BASE + 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .micd_rate = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .gpio_defaults = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) [2] = 0x10000, /* AIF3TXLRCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) [3] = 0x4, /* OPCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static struct s3c64xx_spi_csinfo codec_spi_csinfo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .line = S3C64XX_GPN(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static struct spi_board_info wm5102_reva_spi_devs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .modalias = "wm5102",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .max_speed_hz = 10 * 1000 * 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .bus_num = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .chip_select = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .mode = SPI_MODE_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .irq = GLENFARCLAS_PMIC_IRQ_BASE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) WM831X_IRQ_GPIO_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .controller_data = &codec_spi_csinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .platform_data = &wm5102_reva_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static struct gpiod_lookup_table wm5102_reva_gpiod_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .dev_id = "spi0.1", /* SPI device name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) GPIO_LOOKUP("GPION", 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) "wlf,ldoena", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static struct arizona_pdata wm5102_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .gpio_base = CODEC_GPIO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .irq_flags = IRQF_TRIGGER_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .micd_pol_gpio = CODEC_GPIO_BASE + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .gpio_defaults = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) [2] = 0x10000, /* AIF3TXLRCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) [3] = 0x4, /* OPCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static struct spi_board_info wm5102_spi_devs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .modalias = "wm5102",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .max_speed_hz = 10 * 1000 * 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .bus_num = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .chip_select = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .mode = SPI_MODE_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .irq = GLENFARCLAS_PMIC_IRQ_BASE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) WM831X_IRQ_GPIO_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .controller_data = &codec_spi_csinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .platform_data = &wm5102_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static struct gpiod_lookup_table wm5102_gpiod_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .dev_id = "spi0.1", /* SPI device name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) GPIO_LOOKUP("GPION", 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) "wlf,ldo1ena", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static struct spi_board_info wm5110_spi_devs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .modalias = "wm5110",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .max_speed_hz = 10 * 1000 * 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .bus_num = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .chip_select = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .mode = SPI_MODE_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .irq = GLENFARCLAS_PMIC_IRQ_BASE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) WM831X_IRQ_GPIO_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .controller_data = &codec_spi_csinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .platform_data = &wm5102_reva_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static const struct i2c_board_info wm6230_i2c_devs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) { I2C_BOARD_INFO("wm9081", 0x6c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .platform_data = &wm9081_pdata, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static struct wm2200_pdata wm2200_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .ldo_ena = S3C64XX_GPN(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .gpio_defaults = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) [2] = 0x0005, /* GPIO3 24.576MHz output clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static const struct i2c_board_info wm2200_i2c[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) { I2C_BOARD_INFO("wm2200", 0x3a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .platform_data = &wm2200_pdata, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u8 rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) const struct i2c_board_info *i2c_devs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) int num_i2c_devs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) const struct spi_board_info *spi_devs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) int num_spi_devs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct gpiod_lookup_table *gpiod_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) } gf_mods[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) { .id = 0x01, .rev = 0xff, .name = "1250-EV1 Springbank" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) { .id = 0x02, .rev = 0xff, .name = "1251-EV1 Jura" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) { .id = 0x03, .rev = 0xff, .name = "1252-EV1 Glenlivet" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) { .id = 0x06, .rev = 0xff, .name = "WM8997-6721-CS96-EV1 Lapraoig" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) { .id = 0x07, .rev = 0xff, .name = "WM5110-6271 Deanston",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .spi_devs = wm5110_spi_devs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .num_spi_devs = ARRAY_SIZE(wm5110_spi_devs) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) { .id = 0x08, .rev = 0xff, .name = "WM8903-6102 Tamdhu" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) { .id = 0x09, .rev = 0xff, .name = "WM1811A-6305 Adelphi" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) { .id = 0x0a, .rev = 0xff, .name = "WM8996-6272 Blackadder" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) { .id = 0x0b, .rev = 0xff, .name = "WM8994-6235 Benromach" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) { .id = 0x11, .rev = 0xff, .name = "6249-EV2 Glenfarclas", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) { .id = 0x14, .rev = 0xff, .name = "6271-EV1 Lochnagar" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) { .id = 0x15, .rev = 0xff, .name = "6320-EV1 Bells",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .i2c_devs = wm6230_i2c_devs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .num_i2c_devs = ARRAY_SIZE(wm6230_i2c_devs) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) { .id = 0x21, .rev = 0xff, .name = "1275-EV1 Mortlach" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) { .id = 0x25, .rev = 0xff, .name = "1274-EV1 Glencadam" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) { .id = 0x31, .rev = 0xff, .name = "1253-EV1 Tomatin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .spi_devs = wm1253_devs, .num_spi_devs = ARRAY_SIZE(wm1253_devs) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) { .id = 0x32, .rev = 0xff, .name = "XXXX-EV1 Caol Illa" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) { .id = 0x33, .rev = 0xff, .name = "XXXX-EV1 Oban" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) { .id = 0x34, .rev = 0xff, .name = "WM0010-6320-CS42 Balblair",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .spi_devs = balblair_devs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .num_spi_devs = ARRAY_SIZE(balblair_devs) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) { .id = 0x39, .rev = 0xff, .name = "1254-EV1 Dallas Dhu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .i2c_devs = wm1254_devs, .num_i2c_devs = ARRAY_SIZE(wm1254_devs) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) { .id = 0x3a, .rev = 0xff, .name = "1259-EV1 Tobermory",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .i2c_devs = wm1259_devs, .num_i2c_devs = ARRAY_SIZE(wm1259_devs) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) { .id = 0x3b, .rev = 0xff, .name = "1255-EV1 Kilchoman",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .i2c_devs = wm1255_devs, .num_i2c_devs = ARRAY_SIZE(wm1255_devs) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) { .id = 0x3c, .rev = 0xff, .name = "1273-EV1 Longmorn" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) { .id = 0x3d, .rev = 0xff, .name = "1277-EV1 Littlemill",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .i2c_devs = wm1277_devs, .num_i2c_devs = ARRAY_SIZE(wm1277_devs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .gpiod_table = &wm8994_gpiod_table },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) { .id = 0x3e, .rev = 0, .name = "WM5102-6271-EV1-CS127 Amrut",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .spi_devs = wm5102_reva_spi_devs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .num_spi_devs = ARRAY_SIZE(wm5102_reva_spi_devs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .gpiod_table = &wm5102_reva_gpiod_table },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) { .id = 0x3e, .rev = -1, .name = "WM5102-6271-EV1-CS127 Amrut",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .spi_devs = wm5102_spi_devs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .num_spi_devs = ARRAY_SIZE(wm5102_spi_devs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .gpiod_table = &wm5102_gpiod_table },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) { .id = 0x3f, .rev = -1, .name = "WM2200-6271-CS90-M-REV1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .i2c_devs = wm2200_i2c, .num_i2c_devs = ARRAY_SIZE(wm2200_i2c) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static int wlf_gf_module_probe(struct i2c_client *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) int ret, i, j, id, rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ret = i2c_smbus_read_byte_data(i2c, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) dev_err(&i2c->dev, "Failed to read ID: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) id = (ret & 0xfe) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) rev = ret & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) for (i = 0; i < ARRAY_SIZE(gf_mods); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (id == gf_mods[i].id && (gf_mods[i].rev == 0xff ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) rev == gf_mods[i].rev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) gpiod_add_lookup_table(&wm5102_reva_gpiod_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) gpiod_add_lookup_table(&wm5102_gpiod_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) gpiod_add_lookup_table(&wm8994_gpiod_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (i < ARRAY_SIZE(gf_mods)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) dev_info(&i2c->dev, "%s revision %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) gf_mods[i].name, rev + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) for (j = 0; j < gf_mods[i].num_i2c_devs; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (IS_ERR(i2c_new_client_device(i2c->adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) &(gf_mods[i].i2c_devs[j]))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) dev_err(&i2c->dev, "Failed to register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) spi_register_board_info(gf_mods[i].spi_devs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) gf_mods[i].num_spi_devs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (gf_mods[i].gpiod_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) gpiod_add_lookup_table(gf_mods[i].gpiod_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) dev_warn(&i2c->dev, "Unknown module ID 0x%x revision %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) id, rev + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static const struct i2c_device_id wlf_gf_module_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) { "wlf-gf-module", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static struct i2c_driver wlf_gf_module_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .name = "wlf-gf-module"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .probe_new = wlf_gf_module_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .id_table = wlf_gf_module_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static int __init wlf_gf_module_register(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (!soc_is_s3c64xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return i2c_add_driver(&wlf_gf_module_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) device_initcall(wlf_gf_module_register);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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