^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright 2003-2008 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // http://www.simtec.co.uk/products/EB2410ITX/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/serial_s3c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/dm9000.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/ata_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/serial_8250.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/mtd/rawnand.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/mtd/nand_ecc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/mtd/partitions.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/platform_data/asoc-s3c24xx_simtec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/platform_data/hwmon-s3c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/platform_data/i2c-s3c2410.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/platform_data/mtd-nand-s3c2410.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <net/ax88796.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <asm/mach/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/platform_data/fb-s3c2410.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include "regs-gpio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include "gpio-samsung.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include "cpu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <linux/soc/samsung/s3c-cpu-freq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include "devs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include "gpio-cfg.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include "bast.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include "s3c24xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include "simtec.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define COPYRIGHT ", Copyright 2004-2008 Simtec Electronics"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* macros for virtual address mods for the io space entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* macros to modify the physical addresses for io space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static struct map_desc bast_iodesc[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* ISA IO areas */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .virtual = (u32)S3C24XX_VA_ISA_BYTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .pfn = PA_CS2(BAST_PA_ISAIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .length = SZ_16M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .virtual = (u32)S3C24XX_VA_ISA_WORD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .pfn = PA_CS3(BAST_PA_ISAIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .length = SZ_16M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* bast CPLD control registers, and external interrupt controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .virtual = (u32)BAST_VA_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .pfn = __phys_to_pfn(BAST_PA_CTRL1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .length = SZ_1M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .virtual = (u32)BAST_VA_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .pfn = __phys_to_pfn(BAST_PA_CTRL2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .length = SZ_1M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .virtual = (u32)BAST_VA_CTRL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .pfn = __phys_to_pfn(BAST_PA_CTRL3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .length = SZ_1M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .virtual = (u32)BAST_VA_CTRL4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .pfn = __phys_to_pfn(BAST_PA_CTRL4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .length = SZ_1M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* PC104 IRQ mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .virtual = (u32)BAST_VA_PC104_IRQREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .pfn = __phys_to_pfn(BAST_PA_PC104_IRQREQ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .length = SZ_1M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .virtual = (u32)BAST_VA_PC104_IRQRAW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .pfn = __phys_to_pfn(BAST_PA_PC104_IRQRAW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .length = SZ_1M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .virtual = (u32)BAST_VA_PC104_IRQMASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .pfn = __phys_to_pfn(BAST_PA_PC104_IRQMASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .length = SZ_1M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* peripheral space... one for each of fast/slow/byte/16bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* note, ide is only decoded in word space, even though some registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * are only 8bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* slow, byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { VA_C2(BAST_VA_ISAIO), PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { VA_C2(BAST_VA_ISAMEM), PA_CS2(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* slow, word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { VA_C3(BAST_VA_ISAIO), PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { VA_C3(BAST_VA_ISAMEM), PA_CS3(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* fast, byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { VA_C4(BAST_VA_ISAIO), PA_CS4(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { VA_C4(BAST_VA_ISAMEM), PA_CS4(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* fast, word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { VA_C5(BAST_VA_ISAIO), PA_CS5(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { VA_C5(BAST_VA_ISAMEM), PA_CS5(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .hwport = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .ucon = UCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .ulcon = ULCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .ufcon = UFCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .hwport = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .ucon = UCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .ulcon = ULCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .ufcon = UFCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* port 2 is not actually used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .hwport = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .ucon = UCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .ulcon = ULCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .ufcon = UFCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* NAND Flash on BAST board */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int bast_pm_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* ensure that an nRESET is not generated on resume. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) gpio_direction_output(S3C2410_GPA(21), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static void bast_pm_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define bast_pm_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define bast_pm_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static struct syscore_ops bast_pm_syscore_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .suspend = bast_pm_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .resume = bast_pm_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static int smartmedia_map[] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static int chip0_map[] = { 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static int chip1_map[] = { 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static int chip2_map[] = { 3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static struct mtd_partition __initdata bast_default_nand_part[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .name = "Boot Agent",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .size = SZ_16K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .name = "/boot",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .size = SZ_4M - SZ_16K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .offset = SZ_16K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .name = "user",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .offset = SZ_4M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .size = MTDPART_SIZ_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* the bast has 4 selectable slots for nand-flash, the three
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * on-board chip areas, as well as the external SmartMedia
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * slot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * Note, there is no current hot-plug support for the SmartMedia
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * socket.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static struct s3c2410_nand_set __initdata bast_nand_sets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .name = "SmartMedia",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .nr_chips = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .nr_map = smartmedia_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .options = NAND_SCAN_SILENT_NODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .partitions = bast_default_nand_part,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .name = "chip0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .nr_chips = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .nr_map = chip0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .partitions = bast_default_nand_part,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .name = "chip1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .nr_chips = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .nr_map = chip1_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .options = NAND_SCAN_SILENT_NODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .partitions = bast_default_nand_part,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) [3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .name = "chip2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .nr_chips = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .nr_map = chip2_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .options = NAND_SCAN_SILENT_NODEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .nr_partitions = ARRAY_SIZE(bast_default_nand_part),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .partitions = bast_default_nand_part,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) slot = set->nr_map[slot] & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) slot, set, set->nr_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) tmp = __raw_readb(BAST_VA_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) tmp &= BAST_CPLD_CTLR2_IDERST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) tmp |= slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) tmp |= BAST_CPLD_CTRL2_WNAND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) pr_debug("bast_nand: ctrl2 now %02x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) __raw_writeb(tmp, BAST_VA_CTRL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static struct s3c2410_platform_nand __initdata bast_nand_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .tacls = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .twrph0 = 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .twrph1 = 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .nr_sets = ARRAY_SIZE(bast_nand_sets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .sets = bast_nand_sets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .select_chip = bast_nand_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* DM9000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static struct resource bast_dm9k_resource[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) [1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_DM9000 + 0x40, 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) [2] = DEFINE_RES_NAMED(BAST_IRQ_DM9000 , 1, NULL, IORESOURCE_IRQ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) | IORESOURCE_IRQ_HIGHLEVEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* for the moment we limit ourselves to 16bit IO until some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * better IO routines can be written and tested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static struct dm9000_plat_data bast_dm9k_platdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .flags = DM9000_PLATF_16BITONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static struct platform_device bast_device_dm9k = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .name = "dm9000",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .num_resources = ARRAY_SIZE(bast_dm9k_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .resource = bast_dm9k_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .platform_data = &bast_dm9k_platdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* serial devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define SERIAL_BASE (S3C2410_CS2 + BAST_PA_SUPERIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define SERIAL_CLK (1843200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static struct plat_serial8250_port bast_sio_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .mapbase = SERIAL_BASE + 0x2f8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .irq = BAST_IRQ_PCSERIAL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .flags = SERIAL_FLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .iotype = UPIO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .regshift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .uartclk = SERIAL_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .mapbase = SERIAL_BASE + 0x3f8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .irq = BAST_IRQ_PCSERIAL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .flags = SERIAL_FLAGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .iotype = UPIO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .regshift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .uartclk = SERIAL_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static struct platform_device bast_sio = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .name = "serial8250",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .id = PLAT8250_DEV_PLATFORM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .platform_data = &bast_sio_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* we have devices on the bus which cannot work much over the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * standard 100KHz i2c bus frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static struct s3c2410_platform_i2c __initdata bast_i2c_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .slave_addr = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .frequency = 100*1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* Asix AX88796 10/100 ethernet controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static struct ax_plat_data bast_asix_platdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .flags = AXFLG_MAC_FROMDEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .wordlength = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .dcr_val = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .rcr_val = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static struct resource bast_asix_resource[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET, 0x18 * 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) [1] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET + (0x1f * 0x20), 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) [2] = DEFINE_RES_IRQ(BAST_IRQ_ASIX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static struct platform_device bast_device_asix = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .name = "ax88796",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .num_resources = ARRAY_SIZE(bast_asix_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .resource = bast_asix_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .platform_data = &bast_asix_platdata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* Asix AX88796 10/100 ethernet controller parallel port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static struct resource bast_asixpp_resource[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) [0] = DEFINE_RES_MEM(S3C2410_CS5 + BAST_PA_ASIXNET + (0x18 * 0x20), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 0x30 * 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static struct platform_device bast_device_axpp = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .name = "ax88796-pp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .num_resources = ARRAY_SIZE(bast_asixpp_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .resource = bast_asixpp_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* LCD/VGA controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static struct s3c2410fb_display __initdata bast_lcd_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .type = S3C2410_LCDCON1_TFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .width = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .height = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .pixclock = 33333,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .xres = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .yres = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .bpp = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .left_margin = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .right_margin = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .hsync_len = 88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .upper_margin = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .lower_margin = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .vsync_len = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .lcdcon5 = 0x00014b02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .type = S3C2410_LCDCON1_TFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .width = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .height = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .pixclock = 33333,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .xres = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .yres = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .bpp = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .left_margin = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .right_margin = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .hsync_len = 88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .upper_margin = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .lower_margin = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .vsync_len = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .lcdcon5 = 0x00014b02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .type = S3C2410_LCDCON1_TFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .width = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .height = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .pixclock = 33333,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .xres = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .yres = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .bpp = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .left_margin = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .right_margin = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .hsync_len = 88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .upper_margin = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .lower_margin = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .vsync_len = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .lcdcon5 = 0x00014b02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* LCD/VGA controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static struct s3c2410fb_mach_info __initdata bast_fb_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .displays = bast_lcd_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .num_displays = ARRAY_SIZE(bast_lcd_info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .default_display = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* I2C devices fitted. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static struct i2c_board_info bast_i2c_devs[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) I2C_BOARD_INFO("tlv320aic23", 0x1a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) I2C_BOARD_INFO("simtec-pmu", 0x6b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) I2C_BOARD_INFO("ch7013", 0x75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static struct s3c_hwmon_pdata bast_hwmon_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* LCD contrast (0-6.6V) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .in[0] = &(struct s3c_hwmon_chcfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .name = "lcd-contrast",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .mult = 3300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .div = 512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* LED current feedback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .in[1] = &(struct s3c_hwmon_chcfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .name = "led-feedback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .mult = 3300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .div = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* LCD feedback (0-6.6V) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .in[2] = &(struct s3c_hwmon_chcfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .name = "lcd-feedback",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .mult = 3300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .div = 512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* Vcore (1.8-2.0V), Vref 3.3V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .in[3] = &(struct s3c_hwmon_chcfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .name = "vcore",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .mult = 3300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .div = 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* Standard BAST devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) // cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static struct platform_device *bast_devices[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) &s3c2410_device_dclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) &s3c_device_ohci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) &s3c_device_lcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) &s3c_device_wdt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) &s3c_device_i2c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) &s3c_device_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) &s3c_device_nand,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) &s3c_device_adc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) &s3c_device_hwmon,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) &bast_device_dm9k,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) &bast_device_asix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) &bast_device_axpp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) &bast_sio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static struct s3c_cpufreq_board __initdata bast_cpufreq = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .refresh = 7800, /* 7.8usec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .auto_io = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .need_io = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static struct s3c24xx_audio_simtec_pdata __initdata bast_audio = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .have_mic = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .have_lout = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static void __init bast_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) s3c_hwmon_set_platdata(&bast_hwmon_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static void __init bast_init_time(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) s3c2410_init_clocks(12000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) s3c24xx_timer_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static void __init bast_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) register_syscore_ops(&bast_pm_syscore_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) s3c_i2c0_set_platdata(&bast_i2c_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) s3c_nand_set_platdata(&bast_nand_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) s3c24xx_fb_set_platdata(&bast_fb_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) i2c_register_board_info(0, bast_i2c_devs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) ARRAY_SIZE(bast_i2c_devs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) usb_simtec_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) nor_simtec_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) simtec_audio_add(NULL, true, &bast_audio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) WARN_ON(gpio_request(S3C2410_GPA(21), "bast nreset"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) s3c_cpufreq_setboard(&bast_cpufreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) MACHINE_START(BAST, "Simtec-BAST")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .atag_offset = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .map_io = bast_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .init_irq = s3c2410_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .init_machine = bast_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .init_time = bast_init_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) MACHINE_END
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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