^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright 2008 Openmoko, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // Copyright 2008 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // http://armlinux.simtec.co.uk/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) // Copyright 2009 Kwangwoo Lee
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) // Kwangwoo Lee <kwangwoo.lee@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/serial_s3c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/dm9000.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <video/platform_lcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <video/samsung_fimd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/mach/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include "map.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/platform_data/i2c-s3c2410.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include "fb.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include "devs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include "cpu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <mach/irqs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include "regs-gpio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include "gpio-samsung.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include "s3c64xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include "regs-modem-s3c64xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* DM9000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ANW6410_PA_DM9000 (0x18000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* A hardware buffer to control external devices is mapped at 0x30000000.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * It can not be read. So current status must be kept in anw6410_extdev_status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ANW6410_VA_EXTDEV S3C_ADDR(0x02000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ANW6410_PA_EXTDEV (0x30000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ANW6410_EN_DM9000 (1<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ANW6410_EN_LCD (1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static __u32 anw6410_extdev_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static struct s3c2410_uartcfg anw6410_uartcfgs[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .hwport = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .ucon = 0x3c5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .ulcon = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .ufcon = 0x51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .hwport = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .ucon = 0x3c5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .ulcon = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .ufcon = 0x51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* framebuffer and LCD setup. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static void __init anw6410_lcd_mode_set(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* set the LCD type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) tmp = __raw_readl(S3C64XX_SPCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) tmp &= ~S3C64XX_SPCON_LCD_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) tmp |= S3C64XX_SPCON_LCD_SEL_RGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) __raw_writel(tmp, S3C64XX_SPCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* remove the LCD bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) tmp = __raw_readl(S3C64XX_MODEM_MIFPCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) tmp &= ~MIFPCON_LCD_BYPASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) __raw_writel(tmp, S3C64XX_MODEM_MIFPCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* GPF1 = LCD panel power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * GPF4 = LCD backlight control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static void anw6410_lcd_power_set(struct plat_lcd_data *pd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned int power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (power) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) anw6410_extdev_status |= (ANW6410_EN_LCD << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) __raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) gpio_direction_output(S3C64XX_GPF(1), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) gpio_direction_output(S3C64XX_GPF(4), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) anw6410_extdev_status &= ~(ANW6410_EN_LCD << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) __raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) gpio_direction_output(S3C64XX_GPF(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) gpio_direction_output(S3C64XX_GPF(4), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static struct plat_lcd_data anw6410_lcd_power_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .set_power = anw6410_lcd_power_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static struct platform_device anw6410_lcd_powerdev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .name = "platform-lcd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .dev.parent = &s3c_device_fb.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .dev.platform_data = &anw6410_lcd_power_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static struct s3c_fb_pd_win anw6410_fb_win0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .max_bpp = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .default_bpp = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .xres = 800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .yres = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static struct fb_videomode anw6410_lcd_timing = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .left_margin = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .right_margin = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .upper_margin = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .lower_margin = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .hsync_len = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .vsync_len = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .xres = 800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .yres = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static struct s3c_fb_platdata anw6410_lcd_pdata __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .vtiming = &anw6410_lcd_timing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .win[0] = &anw6410_fb_win0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* DM9000AEP 10/100 ethernet controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static void __init anw6410_dm9000_enable(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) anw6410_extdev_status |= (ANW6410_EN_DM9000 << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) __raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static struct resource anw6410_dm9000_resource[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) [0] = DEFINE_RES_MEM(ANW6410_PA_DM9000, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) [1] = DEFINE_RES_MEM(ANW6410_PA_DM9000 + 4, 501),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) [2] = DEFINE_RES_NAMED(IRQ_EINT(15), 1, NULL, IORESOURCE_IRQ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) | IRQF_TRIGGER_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static struct dm9000_plat_data anw6410_dm9000_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* dev_addr can be set to provide hwaddr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static struct platform_device anw6410_device_eth = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .name = "dm9000",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .num_resources = ARRAY_SIZE(anw6410_dm9000_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .resource = anw6410_dm9000_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .platform_data = &anw6410_dm9000_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static struct map_desc anw6410_iodesc[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .virtual = (unsigned long)ANW6410_VA_EXTDEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .pfn = __phys_to_pfn(ANW6410_PA_EXTDEV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .length = SZ_64K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static struct platform_device *anw6410_devices[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) &s3c_device_fb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) &anw6410_lcd_powerdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) &anw6410_device_eth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static void __init anw6410_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) s3c64xx_init_io(anw6410_iodesc, ARRAY_SIZE(anw6410_iodesc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) s3c64xx_set_xtal_freq(12000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) s3c24xx_init_uarts(anw6410_uartcfgs, ARRAY_SIZE(anw6410_uartcfgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) s3c64xx_set_timer_source(S3C64XX_PWM3, S3C64XX_PWM4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) anw6410_lcd_mode_set();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static void __init anw6410_machine_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) s3c_fb_set_platdata(&anw6410_lcd_pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) gpio_request(S3C64XX_GPF(1), "panel power");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) gpio_request(S3C64XX_GPF(4), "LCD backlight");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) anw6410_dm9000_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) platform_add_devices(anw6410_devices, ARRAY_SIZE(anw6410_devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) MACHINE_START(ANW6410, "A&W6410")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* Maintainer: Kwangwoo Lee <kwangwoo.lee@gmail.com> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .atag_offset = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .nr_irqs = S3C64XX_NR_IRQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .init_irq = s3c6410_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .map_io = anw6410_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .init_machine = anw6410_machine_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .init_time = s3c64xx_timer_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) MACHINE_END
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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