^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright 2003-2009 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // http://armlinux.simtec.co.uk/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/serial_core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/serial_s3c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/ata_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/sm501.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/sm501-regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/mach/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "regs-gpio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "gpio-samsung.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/platform_data/mtd-nand-s3c2410.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/platform_data/i2c-s3c2410.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/mtd/rawnand.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/mtd/nand_ecc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/mtd/partitions.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <net/ax88796.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include "devs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include "cpu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/platform_data/asoc-s3c24xx_simtec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include "anubis.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include "s3c24xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include "simtec.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define COPYRIGHT ", Copyright 2005-2009 Simtec Electronics"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static struct map_desc anubis_iodesc[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* ISA IO areas */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .virtual = (u32)S3C24XX_VA_ISA_BYTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .pfn = __phys_to_pfn(0x0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .length = SZ_4M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .virtual = (u32)S3C24XX_VA_ISA_WORD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .pfn = __phys_to_pfn(0x0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .length = SZ_4M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* we could possibly compress the next set down into a set of smaller tables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * pagetables, but that would mean using an L2 section, and it still means
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * we cannot actually feed the same register to an LDR due to 16K spacing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* CPLD control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .virtual = (u32)ANUBIS_VA_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .pfn = __phys_to_pfn(ANUBIS_PA_CTRL1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .length = SZ_4K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .virtual = (u32)ANUBIS_VA_IDREG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .pfn = __phys_to_pfn(ANUBIS_PA_IDREG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .length = SZ_4K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .hwport = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .ucon = UCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .ulcon = ULCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .ufcon = UFCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .hwport = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .ucon = UCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .ulcon = ULCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .ufcon = UFCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* NAND Flash on Anubis board */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static int external_map[] = { 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int chip0_map[] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static int chip1_map[] = { 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static struct mtd_partition __initdata anubis_default_nand_part[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .name = "Boot Agent",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .size = SZ_16K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .name = "/boot",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .size = SZ_4M - SZ_16K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .offset = SZ_16K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .name = "user1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .offset = SZ_4M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .size = SZ_32M - SZ_4M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) [3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .name = "user2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .offset = SZ_32M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .size = MTDPART_SIZ_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static struct mtd_partition __initdata anubis_default_nand_part_large[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .name = "Boot Agent",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .size = SZ_128K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .name = "/boot",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .size = SZ_4M - SZ_128K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .offset = SZ_128K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .name = "user1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .offset = SZ_4M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .size = SZ_32M - SZ_4M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) [3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .name = "user2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .offset = SZ_32M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .size = MTDPART_SIZ_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* the Anubis has 3 selectable slots for nand-flash, the two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * on-board chip areas, as well as the external slot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * Note, there is no current hot-plug support for the External
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * socket.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static struct s3c2410_nand_set __initdata anubis_nand_sets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .name = "External",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .nr_chips = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .nr_map = external_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .partitions = anubis_default_nand_part,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .name = "chip0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .nr_chips = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .nr_map = chip0_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .partitions = anubis_default_nand_part,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .name = "chip1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .nr_chips = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .nr_map = chip1_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .partitions = anubis_default_nand_part,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static void anubis_nand_select(struct s3c2410_nand_set *set, int slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) slot = set->nr_map[slot] & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) pr_debug("anubis_nand: selecting slot %d (set %p,%p)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) slot, set, set->nr_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) tmp = __raw_readb(ANUBIS_VA_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) tmp &= ~ANUBIS_CTRL1_NANDSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) tmp |= slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) pr_debug("anubis_nand: ctrl1 now %02x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) __raw_writeb(tmp, ANUBIS_VA_CTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static struct s3c2410_platform_nand __initdata anubis_nand_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .tacls = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .twrph0 = 55,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .twrph1 = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .nr_sets = ARRAY_SIZE(anubis_nand_sets),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .sets = anubis_nand_sets,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .select_chip = anubis_nand_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .engine_type = NAND_ECC_ENGINE_TYPE_SOFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* IDE channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static struct pata_platform_info anubis_ide_platdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .ioport_shift = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static struct resource anubis_ide0_resource[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) [0] = DEFINE_RES_MEM(S3C2410_CS3, 8 * 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) [2] = DEFINE_RES_MEM(S3C2410_CS3 + (1 << 26) + (6 * 32), 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) [3] = DEFINE_RES_IRQ(ANUBIS_IRQ_IDE0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static struct platform_device anubis_device_ide0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .name = "pata_platform",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .num_resources = ARRAY_SIZE(anubis_ide0_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .resource = anubis_ide0_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .platform_data = &anubis_ide_platdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .coherent_dma_mask = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static struct resource anubis_ide1_resource[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) [0] = DEFINE_RES_MEM(S3C2410_CS4, 8 * 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) [1] = DEFINE_RES_MEM(S3C2410_CS4 + (1 << 26) + (6 * 32), 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) [2] = DEFINE_RES_IRQ(ANUBIS_IRQ_IDE0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static struct platform_device anubis_device_ide1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .name = "pata_platform",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .num_resources = ARRAY_SIZE(anubis_ide1_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .resource = anubis_ide1_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .platform_data = &anubis_ide_platdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .coherent_dma_mask = ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* Asix AX88796 10/100 ethernet controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static struct ax_plat_data anubis_asix_platdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .flags = AXFLG_MAC_FROMDEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .wordlength = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .dcr_val = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .rcr_val = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static struct resource anubis_asix_resource[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) [0] = DEFINE_RES_MEM(S3C2410_CS5, 0x20 * 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) [1] = DEFINE_RES_IRQ(ANUBIS_IRQ_ASIX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static struct platform_device anubis_device_asix = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .name = "ax88796",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .num_resources = ARRAY_SIZE(anubis_asix_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .resource = anubis_asix_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .platform_data = &anubis_asix_platdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* SM501 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static struct resource anubis_sm501_resource[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) [0] = DEFINE_RES_MEM(S3C2410_CS2, SZ_8M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) [1] = DEFINE_RES_MEM(S3C2410_CS2 + SZ_64M - SZ_2M, SZ_2M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) [2] = DEFINE_RES_IRQ(IRQ_EINT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static struct sm501_initdata anubis_sm501_initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .gpio_high = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .set = 0x3F000000, /* 24bit panel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .mask = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .misc_timing = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .set = 0x010100, /* SDRAM timing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .mask = 0x1F1F00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .misc_control = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .set = SM501_MISC_PNL_24BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .devices = SM501_USE_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* set the SDRAM and bus clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .mclk = 72 * MHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .m1xclk = 144 * MHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static struct sm501_platdata_gpio_i2c anubis_sm501_gpio_i2c[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .bus_num = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .pin_scl = 44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .pin_sda = 45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .bus_num = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .pin_scl = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .pin_sda = 41,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static struct sm501_platdata anubis_sm501_platdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .init = &anubis_sm501_initdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .gpio_base = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .gpio_i2c = anubis_sm501_gpio_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .gpio_i2c_nr = ARRAY_SIZE(anubis_sm501_gpio_i2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static struct platform_device anubis_device_sm501 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .name = "sm501",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .num_resources = ARRAY_SIZE(anubis_sm501_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .resource = anubis_sm501_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .platform_data = &anubis_sm501_platdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* Standard Anubis devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static struct platform_device *anubis_devices[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) &s3c2410_device_dclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) &s3c_device_ohci,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) &s3c_device_wdt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) &s3c_device_adc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) &s3c_device_i2c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) &s3c_device_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) &s3c_device_nand,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) &anubis_device_ide0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) &anubis_device_ide1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) &anubis_device_asix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) &anubis_device_sm501,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* I2C devices. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static struct i2c_board_info anubis_i2c_devs[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) I2C_BOARD_INFO("tps65011", 0x48),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .irq = IRQ_EINT20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* Audio setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static struct s3c24xx_audio_simtec_pdata __initdata anubis_audio = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .have_mic = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .have_lout = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .output_cdclk = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .use_mpllin = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .amp_gpio = S3C2410_GPB(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .amp_gain[0] = S3C2410_GPD(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .amp_gain[1] = S3C2410_GPD(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static void __init anubis_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) s3c24xx_set_timer_source(S3C24XX_PWM3, S3C24XX_PWM4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* check for the newer revision boards with large page nand */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if ((__raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK) >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) printk(KERN_INFO "ANUBIS-B detected (revision %d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) __raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) anubis_nand_sets[0].partitions = anubis_default_nand_part_large;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) anubis_nand_sets[0].nr_partitions = ARRAY_SIZE(anubis_default_nand_part_large);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* ensure that the GPIO is setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) gpio_request_one(S3C2410_GPA(0), GPIOF_OUT_INIT_HIGH, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) gpio_free(S3C2410_GPA(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static void __init anubis_init_time(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) s3c2440_init_clocks(12000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) s3c24xx_timer_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static void __init anubis_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) s3c_i2c0_set_platdata(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) s3c_nand_set_platdata(&anubis_nand_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) simtec_audio_add(NULL, false, &anubis_audio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) i2c_register_board_info(0, anubis_i2c_devs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ARRAY_SIZE(anubis_i2c_devs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) MACHINE_START(ANUBIS, "Simtec-Anubis")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .atag_offset = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .map_io = anubis_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .init_machine = anubis_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .init_irq = s3c2440_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .init_time = anubis_init_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) MACHINE_END
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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