^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (c) 2003-2004 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // http://armlinux.simtec.co.uk/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) // S3C24XX - IRQ PM code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "cpu.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "pm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <mach/map-base.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "map-s3c.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "regs-irq.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "regs-gpio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "pm-core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) int s3c_irq_wake(struct irq_data *data, unsigned int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) unsigned long irqbit = 1 << data->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) if (!(s3c_irqwake_intallow & irqbit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) pr_info("wake %s for hwirq %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) state ? "enabled" : "disabled", data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) if (!state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) s3c_irqwake_intmask |= irqbit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) s3c_irqwake_intmask &= ~irqbit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static struct sleep_save irq_save[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) SAVE_ITEM(S3C2410_INTMSK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) SAVE_ITEM(S3C2410_INTSUBMSK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* the extint values move between the s3c2410/s3c2440 and the s3c2412
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * so we use an array to hold them, and to calculate the address of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * the register at run-time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static unsigned long save_extint[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static unsigned long save_eintflt[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static unsigned long save_eintmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static int s3c24xx_irq_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) for (i = 0; i < ARRAY_SIZE(save_extint); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) save_extint[i] = __raw_readl(S3C24XX_EXTINT0 + (i*4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) save_eintflt[i] = __raw_readl(S3C24XX_EINFLT0 + (i*4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) save_eintmask = __raw_readl(S3C24XX_EINTMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static void s3c24xx_irq_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) for (i = 0; i < ARRAY_SIZE(save_extint); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) __raw_writel(save_extint[i], S3C24XX_EXTINT0 + (i*4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) __raw_writel(save_eintflt[i], S3C24XX_EINFLT0 + (i*4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) __raw_writel(save_eintmask, S3C24XX_EINTMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct syscore_ops s3c24xx_irq_syscore_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .suspend = s3c24xx_irq_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .resume = s3c24xx_irq_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #ifdef CONFIG_CPU_S3C2416
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static struct sleep_save s3c2416_irq_save[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) SAVE_ITEM(S3C2416_INTMSK2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static int s3c2416_irq_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) s3c_pm_do_save(s3c2416_irq_save, ARRAY_SIZE(s3c2416_irq_save));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static void s3c2416_irq_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) s3c_pm_do_restore(s3c2416_irq_save, ARRAY_SIZE(s3c2416_irq_save));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct syscore_ops s3c2416_irq_syscore_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .suspend = s3c2416_irq_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .resume = s3c2416_irq_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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