Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright 2006 Ben Dooks <ben-linux@fluff.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (c) 2005 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *	http://armlinux.simtec.co.uk/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *	Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * iPAQ H1940 series definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef __MACH_S3C24XX_H1940_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define __MACH_S3C24XX_H1940_H __FILE__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define H1940_SUSPEND_CHECKSUM		(0x30003ff8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define H1940_SUSPEND_RESUMEAT		(0x30081000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define H1940_SUSPEND_CHECK		(0x30080000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct gpio_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) extern void h1940_pm_return(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) extern int h1940_led_blink_set(struct gpio_desc *desc, int state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 			       unsigned long *delay_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 			       unsigned long *delay_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define H1940_LATCH_GPIO(x)		(S3C_GPIO_END + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* SD layer latch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define H1940_LATCH_LCD_P0		H1940_LATCH_GPIO(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define H1940_LATCH_LCD_P1		H1940_LATCH_GPIO(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define H1940_LATCH_LCD_P2		H1940_LATCH_GPIO(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define H1940_LATCH_LCD_P3		H1940_LATCH_GPIO(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define H1940_LATCH_MAX1698_nSHUTDOWN	H1940_LATCH_GPIO(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define H1940_LATCH_LED_RED		H1940_LATCH_GPIO(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define H1940_LATCH_SDQ7		H1940_LATCH_GPIO(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define H1940_LATCH_USB_DP		H1940_LATCH_GPIO(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* CPU layer latch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define H1940_LATCH_UDA_POWER		H1940_LATCH_GPIO(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define H1940_LATCH_AUDIO_POWER		H1940_LATCH_GPIO(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define H1940_LATCH_SM803_ENABLE	H1940_LATCH_GPIO(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define H1940_LATCH_LCD_P4		H1940_LATCH_GPIO(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define H1940_LATCH_SD_POWER		H1940_LATCH_GPIO(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define H1940_LATCH_BLUETOOTH_POWER	H1940_LATCH_GPIO(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define H1940_LATCH_LED_GREEN		H1940_LATCH_GPIO(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define H1940_LATCH_LED_FLASH		H1940_LATCH_GPIO(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #endif /* __MACH_S3C24XX_H1940_H */