^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2008 Openmoko, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2008 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * http://armlinux.simtec.co.uk/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * S3C6400 - GPIO lib support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef GPIO_SAMSUNG_S3C64XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define GPIO_SAMSUNG_S3C64XX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #ifdef CONFIG_GPIO_SAMSUNG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* GPIO bank sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define S3C64XX_GPIO_A_NR (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define S3C64XX_GPIO_B_NR (7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define S3C64XX_GPIO_C_NR (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define S3C64XX_GPIO_D_NR (5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define S3C64XX_GPIO_E_NR (5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define S3C64XX_GPIO_F_NR (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define S3C64XX_GPIO_G_NR (7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define S3C64XX_GPIO_H_NR (10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define S3C64XX_GPIO_I_NR (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define S3C64XX_GPIO_J_NR (12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define S3C64XX_GPIO_K_NR (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define S3C64XX_GPIO_L_NR (15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define S3C64XX_GPIO_M_NR (6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define S3C64XX_GPIO_N_NR (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define S3C64XX_GPIO_O_NR (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define S3C64XX_GPIO_P_NR (15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define S3C64XX_GPIO_Q_NR (9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* GPIO bank numbes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* CONFIG_S3C_GPIO_SPACE allows the user to select extra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * space for debugging purposes so that any accidental
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * change from one gpio bank to another can be caught.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define S3C64XX_GPIO_NEXT(__gpio) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) enum s3c_gpio_number {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) S3C64XX_GPIO_A_START = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) S3C64XX_GPIO_B_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) S3C64XX_GPIO_C_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) S3C64XX_GPIO_D_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) S3C64XX_GPIO_E_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) S3C64XX_GPIO_F_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_E),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) S3C64XX_GPIO_G_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) S3C64XX_GPIO_H_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_G),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) S3C64XX_GPIO_I_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_H),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) S3C64XX_GPIO_J_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_I),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) S3C64XX_GPIO_K_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_J),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) S3C64XX_GPIO_L_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_K),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) S3C64XX_GPIO_M_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_L),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) S3C64XX_GPIO_N_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) S3C64XX_GPIO_O_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) S3C64XX_GPIO_P_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_O),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) S3C64XX_GPIO_Q_START = S3C64XX_GPIO_NEXT(S3C64XX_GPIO_P),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* S3C64XX GPIO number definitions. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define S3C64XX_GPA(_nr) (S3C64XX_GPIO_A_START + (_nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define S3C64XX_GPB(_nr) (S3C64XX_GPIO_B_START + (_nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define S3C64XX_GPC(_nr) (S3C64XX_GPIO_C_START + (_nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define S3C64XX_GPD(_nr) (S3C64XX_GPIO_D_START + (_nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define S3C64XX_GPE(_nr) (S3C64XX_GPIO_E_START + (_nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define S3C64XX_GPF(_nr) (S3C64XX_GPIO_F_START + (_nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define S3C64XX_GPG(_nr) (S3C64XX_GPIO_G_START + (_nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define S3C64XX_GPH(_nr) (S3C64XX_GPIO_H_START + (_nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define S3C64XX_GPI(_nr) (S3C64XX_GPIO_I_START + (_nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define S3C64XX_GPJ(_nr) (S3C64XX_GPIO_J_START + (_nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define S3C64XX_GPK(_nr) (S3C64XX_GPIO_K_START + (_nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define S3C64XX_GPL(_nr) (S3C64XX_GPIO_L_START + (_nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define S3C64XX_GPM(_nr) (S3C64XX_GPIO_M_START + (_nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define S3C64XX_GPN(_nr) (S3C64XX_GPIO_N_START + (_nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define S3C64XX_GPO(_nr) (S3C64XX_GPIO_O_START + (_nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define S3C64XX_GPP(_nr) (S3C64XX_GPIO_P_START + (_nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define S3C64XX_GPQ(_nr) (S3C64XX_GPIO_Q_START + (_nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* the end of the S3C64XX specific gpios */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define S3C64XX_GPIO_END (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define S3C_GPIO_END S3C64XX_GPIO_END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* define the number of gpios we need to the one after the GPQ() range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define GPIO_BOARD_START (S3C64XX_GPQ(S3C64XX_GPIO_Q_NR) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #endif /* GPIO_SAMSUNG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #endif /* GPIO_SAMSUNG_S3C64XX_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags