Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /* linux/arch/arm/mach-s3c6400/include/mach/dma.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Copyright 2008 Openmoko, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright 2008 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *      Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *      http://armlinux.simtec.co.uk/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * S3C6400 - DMA support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef __ASM_ARCH_DMA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define __ASM_ARCH_DMA_H __FILE__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define S3C64XX_DMA_CHAN(name)		((unsigned long)(name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* DMA0/SDMA0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DMACH_UART0		"uart0_tx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DMACH_UART0_SRC2	"uart0_rx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DMACH_UART1		"uart1_tx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DMACH_UART1_SRC2	"uart1_rx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DMACH_UART2		"uart2_tx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DMACH_UART2_SRC2	"uart2_rx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DMACH_UART3		"uart3_tx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DMACH_UART3_SRC2	"uart3_rx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DMACH_PCM0_TX		"pcm0_tx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DMACH_PCM0_RX		"pcm0_rx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DMACH_I2S0_OUT		"i2s0_tx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DMACH_I2S0_IN		"i2s0_rx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DMACH_SPI0_TX		S3C64XX_DMA_CHAN("spi0_tx")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DMACH_SPI0_RX		S3C64XX_DMA_CHAN("spi0_rx")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DMACH_HSI_I2SV40_TX	"i2s2_tx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DMACH_HSI_I2SV40_RX	"i2s2_rx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* DMA1/SDMA1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DMACH_PCM1_TX		"pcm1_tx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DMACH_PCM1_RX		"pcm1_rx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DMACH_I2S1_OUT		"i2s1_tx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DMACH_I2S1_IN		"i2s1_rx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DMACH_SPI1_TX		S3C64XX_DMA_CHAN("spi1_tx")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DMACH_SPI1_RX		S3C64XX_DMA_CHAN("spi1_rx")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DMACH_AC97_PCMOUT	"ac97_out"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DMACH_AC97_PCMIN	"ac97_in"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DMACH_AC97_MICIN	"ac97_mic"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DMACH_PWM		"pwm"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DMACH_IRDA		"irda"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DMACH_EXTERNAL		"external"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DMACH_SECURITY_RX	"sec_rx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DMACH_SECURITY_TX	"sec_tx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) enum dma_ch {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	DMACH_MAX = 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <linux/amba/pl08x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #endif /* __ASM_ARCH_IRQ_H */