Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2003-2006 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *	Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Samsung S3C24XX DMA support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #ifndef __ASM_ARCH_DMA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __ASM_ARCH_DMA_H __FILE__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* We use `virtual` dma channels to hide the fact we have only a limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * number of DMA channels, and not of all of them (dependent on the device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  * can be attached to any DMA source. We therefore let the DMA core handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  * the allocation of hardware channels to clients.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) enum dma_ch {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	DMACH_XD0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	DMACH_XD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	DMACH_SDI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	DMACH_SPI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	DMACH_SPI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	DMACH_UART0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	DMACH_UART1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	DMACH_UART2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	DMACH_TIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	DMACH_I2S_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	DMACH_I2S_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	DMACH_PCM_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	DMACH_PCM_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	DMACH_MIC_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	DMACH_USB_EP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	DMACH_USB_EP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	DMACH_USB_EP3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	DMACH_USB_EP4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	DMACH_UART0_SRC2,	/* s3c2412 second uart sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	DMACH_UART1_SRC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	DMACH_UART2_SRC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	DMACH_UART3,		/* s3c2443 has extra uart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	DMACH_UART3_SRC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	DMACH_SPI0_TX,		/* s3c2443/2416/2450 hsspi0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	DMACH_SPI0_RX,		/* s3c2443/2416/2450 hsspi0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	DMACH_SPI1_TX,		/* s3c2443/2450 hsspi1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	DMACH_SPI1_RX,		/* s3c2443/2450 hsspi1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	DMACH_MAX,		/* the end entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #endif /* __ASM_ARCH_DMA_H */