Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) // Copyright (c) 2009 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) //	http://armlinux.simtec.co.uk/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) //	Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) // S3C24XX CPU Frequency scaling - utils for S3C2410/S3C2440/S3C2442
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "map.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "regs-clock.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/soc/samsung/s3c-cpufreq-core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "regs-mem-s3c24xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  * s3c2410_cpufreq_setrefresh - set SDRAM refresh value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  * @cfg: The frequency configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)  * Set the SDRAM refresh value appropriately for the configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)  * frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	struct s3c_cpufreq_board *board = cfg->board;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	unsigned long refresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	unsigned long refval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	/* Reduce both the refresh time (in ns) and the frequency (in MHz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	 * down to ensure that we do not overflow 32 bit numbers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	 * This should work for HCLK up to 133MHz and refresh period up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	 * to 30usec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	refresh = (cfg->freq.hclk / 100) * (board->refresh / 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	refresh = DIV_ROUND_UP(refresh, (1000 * 1000)); /* apply scale  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	refresh = (1 << 11) + 1 - refresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	s3c_freq_dbg("%s: refresh value %lu\n", __func__, refresh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	refval = __raw_readl(S3C2410_REFRESH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	refval &= ~((1 << 12) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	refval |= refresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	__raw_writel(refval, S3C2410_REFRESH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)  * s3c2410_set_fvco - set the PLL value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)  * @cfg: The frequency configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	if (!IS_ERR(cfg->mpll))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		clk_set_rate(cfg->mpll, cfg->pll.frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 s3c2440_read_camdivn(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	return __raw_readl(S3C2440_CAMDIVN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) void s3c2440_write_camdivn(u32 camdiv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	__raw_writel(camdiv, S3C2440_CAMDIVN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 s3c24xx_read_clkdivn(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 	return __raw_readl(S3C2410_CLKDIVN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) void s3c24xx_write_clkdivn(u32 clkdiv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 	__raw_writel(clkdiv, S3C2410_CLKDIVN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 s3c24xx_read_mpllcon(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 	return __raw_readl(S3C2410_MPLLCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) void s3c24xx_write_locktime(u32 locktime)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) 	return __raw_writel(locktime, S3C2410_LOCKTIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }