Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2003-2004 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *	Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * BAST - CPLD control constants
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * BAST - IRQ Number definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * BAST - Memory map definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #ifndef __MACH_S3C24XX_BAST_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define __MACH_S3C24XX_BAST_H __FILE__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) /* CTRL1 - Audio LR routing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define BAST_CPLD_CTRL1_LRCOFF		(0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define BAST_CPLD_CTRL1_LRCADC		(0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define BAST_CPLD_CTRL1_LRCDAC		(0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define BAST_CPLD_CTRL1_LRCARM		(0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define BAST_CPLD_CTRL1_LRMASK		(0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /* CTRL2 - NAND WP control, IDE Reset assert/check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define BAST_CPLD_CTRL2_WNAND		(0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define BAST_CPLD_CTLR2_IDERST		(0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) /* CTRL3 - rom write control, CPLD identity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define BAST_CPLD_CTRL3_IDMASK		(0x0e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define BAST_CPLD_CTRL3_ROMWEN		(0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) /* CTRL4 - 8bit LCD interface control/status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define BAST_CPLD_CTRL4_LLAT		(0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define BAST_CPLD_CTRL4_LCDRW		(0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define BAST_CPLD_CTRL4_LCDCMD		(0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define BAST_CPLD_CTRL4_LCDE2		(0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) /* CTRL5 - DMA routing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define BAST_CPLD_DMA0_PRIIDE		(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define BAST_CPLD_DMA0_SECIDE		(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define BAST_CPLD_DMA0_ISA15		(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define BAST_CPLD_DMA0_ISA36		(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define BAST_CPLD_DMA1_PRIIDE		(0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define BAST_CPLD_DMA1_SECIDE		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define BAST_CPLD_DMA1_ISA15		(2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define BAST_CPLD_DMA1_ISA36		(3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) /* irq numbers to onboard peripherals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define BAST_IRQ_USBOC			IRQ_EINT18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define BAST_IRQ_IDE0			IRQ_EINT16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define BAST_IRQ_IDE1			IRQ_EINT17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define BAST_IRQ_PCSERIAL1		IRQ_EINT15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define BAST_IRQ_PCSERIAL2		IRQ_EINT14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define BAST_IRQ_PCPARALLEL		IRQ_EINT13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define BAST_IRQ_ASIX			IRQ_EINT11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define BAST_IRQ_DM9000			IRQ_EINT10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define BAST_IRQ_ISA			IRQ_EINT9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define BAST_IRQ_SMALERT		IRQ_EINT8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) /* map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  * ok, we've used up to 0x13000000, now we need to find space for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  * peripherals that live in the nGCS[x] areas, which are quite numerous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  * in their space. We also have the board's CPLD to find register space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  * for.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define BAST_IOADDR(x)			(S3C2410_ADDR((x) + 0x01300000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) /* we put the CPLD registers next, to get them out of the way */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define BAST_VA_CTRL1			BAST_IOADDR(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define BAST_PA_CTRL1			(S3C2410_CS5 | 0x7800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define BAST_VA_CTRL2			BAST_IOADDR(0x00100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define BAST_PA_CTRL2			(S3C2410_CS1 | 0x6000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define BAST_VA_CTRL3			BAST_IOADDR(0x00200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define BAST_PA_CTRL3			(S3C2410_CS1 | 0x6800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define BAST_VA_CTRL4			BAST_IOADDR(0x00300000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define BAST_PA_CTRL4			(S3C2410_CS1 | 0x7000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) /* next, we have the PC104 ISA interrupt registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define BAST_PA_PC104_IRQREQ		(S3C2410_CS5 | 0x6000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define BAST_VA_PC104_IRQREQ		BAST_IOADDR(0x00400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define BAST_PA_PC104_IRQRAW		(S3C2410_CS5 | 0x6800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define BAST_VA_PC104_IRQRAW		BAST_IOADDR(0x00500000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define BAST_PA_PC104_IRQMASK		(S3C2410_CS5 | 0x7000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define BAST_VA_PC104_IRQMASK		BAST_IOADDR(0x00600000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define BAST_PA_LCD_RCMD1		(0x8800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define BAST_VA_LCD_RCMD1		BAST_IOADDR(0x00700000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define BAST_PA_LCD_WCMD1		(0x8000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define BAST_VA_LCD_WCMD1		BAST_IOADDR(0x00800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define BAST_PA_LCD_RDATA1		(0x9800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define BAST_VA_LCD_RDATA1		BAST_IOADDR(0x00900000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define BAST_PA_LCD_WDATA1		(0x9000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define BAST_VA_LCD_WDATA1		BAST_IOADDR(0x00A00000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define BAST_PA_LCD_RCMD2		(0xA800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define BAST_VA_LCD_RCMD2		BAST_IOADDR(0x00B00000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define BAST_PA_LCD_WCMD2		(0xA000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define BAST_VA_LCD_WCMD2		BAST_IOADDR(0x00C00000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define BAST_PA_LCD_RDATA2		(0xB800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define BAST_VA_LCD_RDATA2		BAST_IOADDR(0x00D00000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define BAST_PA_LCD_WDATA2		(0xB000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define BAST_VA_LCD_WDATA2		BAST_IOADDR(0x00E00000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)  * 0xE0000000 contains the IO space that is split by speed and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)  * whether the access is for 8 or 16bit IO... this ensures that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)  * the correct access is made
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)  * 0x10000000 of space, partitioned as so:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)  * 0x00000000 to 0x04000000  8bit,  slow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)  * 0x04000000 to 0x08000000  16bit, slow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)  * 0x08000000 to 0x0C000000  16bit, net
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)  * 0x0C000000 to 0x10000000  16bit, fast
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)  * each of these spaces has the following in:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)  * 0x00000000 to 0x01000000 16MB ISA IO space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)  * 0x01000000 to 0x02000000 16MB ISA memory space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)  * 0x02000000 to 0x02100000 1MB  IDE primary channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)  * 0x02100000 to 0x02200000 1MB  IDE primary channel aux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)  * 0x02200000 to 0x02400000 1MB  IDE secondary channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)  * 0x02300000 to 0x02400000 1MB  IDE secondary channel aux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)  * 0x02400000 to 0x02500000 1MB  ASIX ethernet controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)  * 0x02500000 to 0x02600000 1MB  Davicom DM9000 ethernet controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)  * 0x02600000 to 0x02700000 1MB  PC SuperIO controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)  * the phyiscal layout of the zones are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)  *  nGCS2 - 8bit, slow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)  *  nGCS3 - 16bit, slow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)  *  nGCS4 - 16bit, net
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)  *  nGCS5 - 16bit, fast
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define BAST_VA_MULTISPACE		(0xE0000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define BAST_VA_ISAIO			(BAST_VA_MULTISPACE + 0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define BAST_VA_ISAMEM			(BAST_VA_MULTISPACE + 0x01000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define BAST_VA_IDEPRI			(BAST_VA_MULTISPACE + 0x02000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define BAST_VA_IDEPRIAUX		(BAST_VA_MULTISPACE + 0x02100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define BAST_VA_IDESEC			(BAST_VA_MULTISPACE + 0x02200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define BAST_VA_IDESECAUX		(BAST_VA_MULTISPACE + 0x02300000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define BAST_VA_ASIXNET			(BAST_VA_MULTISPACE + 0x02400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define BAST_VA_DM9000			(BAST_VA_MULTISPACE + 0x02500000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define BAST_VA_SUPERIO			(BAST_VA_MULTISPACE + 0x02600000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define BAST_VAM_CS2			(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define BAST_VAM_CS3			(0x04000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define BAST_VAM_CS4			(0x08000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define BAST_VAM_CS5			(0x0C000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* physical offset addresses for the peripherals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define BAST_PA_ISAIO			(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define BAST_PA_ASIXNET			(0x01000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define BAST_PA_SUPERIO			(0x01800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define BAST_PA_IDEPRI			(0x02000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define BAST_PA_IDEPRIAUX		(0x02800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define BAST_PA_IDESEC			(0x03000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define BAST_PA_IDESECAUX		(0x03800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define BAST_PA_ISAMEM			(0x04000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define BAST_PA_DM9000			(0x05000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* some configurations for the peripherals */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define BAST_PCSIO			(BAST_VA_SUPERIO + BAST_VAM_CS2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define BAST_ASIXNET_CS			BAST_VAM_CS5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define BAST_DM9000_CS			BAST_VAM_CS4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define BAST_IDE_CS	S3C2410_CS5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #endif /* __MACH_S3C24XX_BAST_H */