Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2005 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *	http://www.simtec.co.uk/products/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *	Ben Dooks <ben@simtec.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * ANUBIS - CPLD control constants
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * ANUBIS - IRQ Number definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * ANUBIS - Memory map definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef __MACH_S3C24XX_ANUBIS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define __MACH_S3C24XX_ANUBIS_H __FILE__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* CTRL2 - NAND WP control, IDE Reset assert/check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ANUBIS_CTRL1_NANDSEL		(0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* IDREG - revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ANUBIS_IDREG_REVMASK		(0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ANUBIS_IRQ_IDE0			IRQ_EINT2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ANUBIS_IRQ_IDE1			IRQ_EINT3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ANUBIS_IRQ_ASIX			IRQ_EINT1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* start peripherals off after the S3C2410 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ANUBIS_IOADDR(x)		(S3C2410_ADDR((x) + 0x01800000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ANUBIS_PA_CPLD			(S3C2410_CS1 | (1<<26))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* we put the CPLD registers next, to get them out of the way */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ANUBIS_VA_CTRL1			ANUBIS_IOADDR(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ANUBIS_PA_CTRL1			ANUBIS_PA_CPLD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ANUBIS_VA_IDREG			ANUBIS_IOADDR(0x00300000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ANUBIS_PA_IDREG			(ANUBIS_PA_CPLD + (3 << 23))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ANUBIS_IDEPRI			ANUBIS_IOADDR(0x01000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ANUBIS_IDEPRIAUX		ANUBIS_IOADDR(0x01100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ANUBIS_IDESEC			ANUBIS_IOADDR(0x01200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ANUBIS_IDESECAUX		ANUBIS_IOADDR(0x01300000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #endif /* __MACH_S3C24XX_ANUBIS_H */