Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-1.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // Copyright (c) 2008 Simtec Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) //	http://armlinux.simtec.co.uk/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) //	Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) // Samsung ADC device core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include "regs-adc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/soc/samsung/s3c-adc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) /* This driver is designed to control the usage of the ADC block between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * the touchscreen and any other drivers that may need to use it, such as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * the hwmon driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * Priority will be given to the touchscreen driver, but as this itself is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  * rate limited it should not starve other requests which are processed in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * order that they are received.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * Each user registers to get a client block which uniquely identifies it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * and stores information such as the necessary functions to callback when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * action is required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) enum s3c_cpu_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	TYPE_ADCV1, /* S3C24XX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	TYPE_ADCV11, /* S3C2443 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	TYPE_ADCV12, /* S3C2416, S3C2450 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	TYPE_ADCV2, /* S3C64XX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	TYPE_ADCV3, /* S5PV210, S5PC110, Exynos4210 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) struct s3c_adc_client {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	struct platform_device	*pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	struct list_head	 pend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	wait_queue_head_t	*wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	unsigned int		 nr_samples;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	int			 result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	unsigned char		 is_ts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	unsigned char		 channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	void	(*select_cb)(struct s3c_adc_client *c, unsigned selected);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	void	(*convert_cb)(struct s3c_adc_client *c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 			      unsigned val1, unsigned val2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 			      unsigned *samples_left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) struct adc_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	struct platform_device	*pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	struct platform_device	*owner;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	struct clk		*clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	struct s3c_adc_client	*cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	struct s3c_adc_client	*ts_pend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	void __iomem		*regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	spinlock_t		 lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	unsigned int		 prescale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	int			 irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	struct regulator	*vdd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) static struct adc_device *adc_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static LIST_HEAD(adc_pending);	/* protected by adc_device.lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define adc_dbg(_adc, msg...) dev_dbg(&(_adc)->pdev->dev, msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) static inline void s3c_adc_convert(struct adc_device *adc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	unsigned con = readl(adc->regs + S3C2410_ADCCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	con |= S3C2410_ADCCON_ENABLE_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	writel(con, adc->regs + S3C2410_ADCCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) static inline void s3c_adc_select(struct adc_device *adc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 				  struct s3c_adc_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	unsigned con = readl(adc->regs + S3C2410_ADCCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	enum s3c_cpu_type cpu = platform_get_device_id(adc->pdev)->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	client->select_cb(client, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	if (cpu == TYPE_ADCV1 || cpu == TYPE_ADCV2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		con &= ~S3C2410_ADCCON_MUXMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	con &= ~S3C2410_ADCCON_STDBM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	con &= ~S3C2410_ADCCON_STARTMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	if (!client->is_ts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		if (cpu == TYPE_ADCV3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 			writel(client->channel & 0xf, adc->regs + S5P_ADCMUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		else if (cpu == TYPE_ADCV11 || cpu == TYPE_ADCV12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 			writel(client->channel & 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 						adc->regs + S3C2443_ADCMUX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 			con |= S3C2410_ADCCON_SELMUX(client->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	writel(con, adc->regs + S3C2410_ADCCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static void s3c_adc_dbgshow(struct adc_device *adc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	adc_dbg(adc, "CON=%08x, TSC=%08x, DLY=%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		readl(adc->regs + S3C2410_ADCCON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		readl(adc->regs + S3C2410_ADCTSC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		readl(adc->regs + S3C2410_ADCDLY));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static void s3c_adc_try(struct adc_device *adc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	struct s3c_adc_client *next = adc->ts_pend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	if (!next && !list_empty(&adc_pending)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		next = list_first_entry(&adc_pending,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 					struct s3c_adc_client, pend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		list_del(&next->pend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	} else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		adc->ts_pend = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	if (next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		adc_dbg(adc, "new client is %p\n", next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		adc->cur = next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		s3c_adc_select(adc, next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		s3c_adc_convert(adc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		s3c_adc_dbgshow(adc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int s3c_adc_start(struct s3c_adc_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		  unsigned int channel, unsigned int nr_samples)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	struct adc_device *adc = adc_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	if (!adc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		printk(KERN_ERR "%s: failed to find adc\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	spin_lock_irqsave(&adc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	if (client->is_ts && adc->ts_pend) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		spin_unlock_irqrestore(&adc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	client->channel = channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	client->nr_samples = nr_samples;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	if (client->is_ts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		adc->ts_pend = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		list_add_tail(&client->pend, &adc_pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	if (!adc->cur)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		s3c_adc_try(adc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	spin_unlock_irqrestore(&adc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) EXPORT_SYMBOL_GPL(s3c_adc_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static void s3c_convert_done(struct s3c_adc_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 			     unsigned v, unsigned u, unsigned *left)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	client->result = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	wake_up(client->wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int s3c_adc_read(struct s3c_adc_client *client, unsigned int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	DECLARE_WAIT_QUEUE_HEAD_ONSTACK(wake);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	client->convert_cb = s3c_convert_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	client->wait = &wake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	client->result = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	ret = s3c_adc_start(client, ch, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	ret = wait_event_timeout(wake, client->result >= 0, HZ / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	if (client->result < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		ret = -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	client->convert_cb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	return client->result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) EXPORT_SYMBOL_GPL(s3c_adc_read);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static void s3c_adc_default_select(struct s3c_adc_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 				   unsigned select)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct s3c_adc_client *s3c_adc_register(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 					void (*select)(struct s3c_adc_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 						       unsigned int selected),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 					void (*conv)(struct s3c_adc_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 						     unsigned d0, unsigned d1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 						     unsigned *samples_left),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 					unsigned int is_ts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	struct s3c_adc_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	WARN_ON(!pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	if (!select)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		select = s3c_adc_default_select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	if (!pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	client = kzalloc(sizeof(*client), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	if (!client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	client->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	client->is_ts = is_ts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	client->select_cb = select;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	client->convert_cb = conv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	return client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) EXPORT_SYMBOL_GPL(s3c_adc_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) void s3c_adc_release(struct s3c_adc_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	spin_lock_irqsave(&adc_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	/* We should really check that nothing is in progress. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	if (adc_dev->cur == client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		adc_dev->cur = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	if (adc_dev->ts_pend == client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		adc_dev->ts_pend = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		struct list_head *p, *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		struct s3c_adc_client *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		list_for_each_safe(p, n, &adc_pending) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 			tmp = list_entry(p, struct s3c_adc_client, pend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 			if (tmp == client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 				list_del(&tmp->pend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	if (adc_dev->cur == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		s3c_adc_try(adc_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	spin_unlock_irqrestore(&adc_dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	kfree(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) EXPORT_SYMBOL_GPL(s3c_adc_release);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static irqreturn_t s3c_adc_irq(int irq, void *pw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	struct adc_device *adc = pw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	struct s3c_adc_client *client = adc->cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	enum s3c_cpu_type cpu = platform_get_device_id(adc->pdev)->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	unsigned data0, data1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	if (!client) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		dev_warn(&adc->pdev->dev, "%s: no adc pending\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	data0 = readl(adc->regs + S3C2410_ADCDAT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	data1 = readl(adc->regs + S3C2410_ADCDAT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	adc_dbg(adc, "read %d: 0x%04x, 0x%04x\n", client->nr_samples, data0, data1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	client->nr_samples--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	if (cpu == TYPE_ADCV1 || cpu == TYPE_ADCV11) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		data0 &= 0x3ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		data1 &= 0x3ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		/* S3C2416/S3C64XX/S5P ADC resolution is 12-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		data0 &= 0xfff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		data1 &= 0xfff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	if (client->convert_cb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		(client->convert_cb)(client, data0, data1, &client->nr_samples);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	if (client->nr_samples > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		/* fire another conversion for this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		client->select_cb(client, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		s3c_adc_convert(adc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		spin_lock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		(client->select_cb)(client, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		adc->cur = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		s3c_adc_try(adc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		spin_unlock(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	if (cpu == TYPE_ADCV2 || cpu == TYPE_ADCV3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		/* Clear ADC interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		writel(0, adc->regs + S3C64XX_ADCCLRINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static int s3c_adc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	struct adc_device *adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	enum s3c_cpu_type cpu = platform_get_device_id(pdev)->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	unsigned tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	adc = devm_kzalloc(dev, sizeof(*adc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	if (!adc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	spin_lock_init(&adc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	adc->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	adc->prescale = S3C2410_ADCCON_PRSCVL(49);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	adc->vdd = devm_regulator_get(dev, "vdd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	if (IS_ERR(adc->vdd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		dev_err(dev, "operating without regulator \"vdd\" .\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		return PTR_ERR(adc->vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	adc->irq = platform_get_irq(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	if (adc->irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	ret = devm_request_irq(dev, adc->irq, s3c_adc_irq, 0, dev_name(dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 				adc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		dev_err(dev, "failed to attach adc irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	adc->clk = devm_clk_get(dev, "adc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	if (IS_ERR(adc->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		dev_err(dev, "failed to get adc clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		return PTR_ERR(adc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	adc->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	if (IS_ERR(adc->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		return PTR_ERR(adc->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	ret = regulator_enable(adc->vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	clk_prepare_enable(adc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	tmp = adc->prescale | S3C2410_ADCCON_PRSCEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	/* Enable 12-bit ADC resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	if (cpu == TYPE_ADCV12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		tmp |= S3C2416_ADCCON_RESSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	if (cpu == TYPE_ADCV2 || cpu == TYPE_ADCV3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		tmp |= S3C64XX_ADCCON_RESSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	writel(tmp, adc->regs + S3C2410_ADCCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	dev_info(dev, "attached adc driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	platform_set_drvdata(pdev, adc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	adc_dev = adc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static int s3c_adc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	struct adc_device *adc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	clk_disable_unprepare(adc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	regulator_disable(adc->vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static int s3c_adc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	struct adc_device *adc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	u32 con;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	spin_lock_irqsave(&adc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	con = readl(adc->regs + S3C2410_ADCCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	con |= S3C2410_ADCCON_STDBM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	writel(con, adc->regs + S3C2410_ADCCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	disable_irq(adc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	spin_unlock_irqrestore(&adc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	clk_disable(adc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	regulator_disable(adc->vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static int s3c_adc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	struct platform_device *pdev = to_platform_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	struct adc_device *adc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	enum s3c_cpu_type cpu = platform_get_device_id(pdev)->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	unsigned long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	ret = regulator_enable(adc->vdd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	clk_enable(adc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	enable_irq(adc->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	tmp = adc->prescale | S3C2410_ADCCON_PRSCEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	/* Enable 12-bit ADC resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	if (cpu == TYPE_ADCV12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 		tmp |= S3C2416_ADCCON_RESSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	if (cpu == TYPE_ADCV2 || cpu == TYPE_ADCV3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 		tmp |= S3C64XX_ADCCON_RESSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	writel(tmp, adc->regs + S3C2410_ADCCON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define s3c_adc_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define s3c_adc_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static const struct platform_device_id s3c_adc_driver_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 		.name           = "s3c24xx-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 		.driver_data    = TYPE_ADCV1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 		.name		= "s3c2443-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 		.driver_data	= TYPE_ADCV11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 		.name		= "s3c2416-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 		.driver_data	= TYPE_ADCV12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 		.name           = "s3c64xx-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 		.driver_data    = TYPE_ADCV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 		.name		= "samsung-adc-v3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 		.driver_data	= TYPE_ADCV3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) MODULE_DEVICE_TABLE(platform, s3c_adc_driver_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static const struct dev_pm_ops adc_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	.suspend	= s3c_adc_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	.resume		= s3c_adc_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static struct platform_driver s3c_adc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	.id_table	= s3c_adc_driver_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 		.name	= "s3c-adc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 		.pm	= &adc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	.probe		= s3c_adc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	.remove		= s3c_adc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static int __init adc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	ret = platform_driver_register(&s3c_adc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 		printk(KERN_ERR "%s: failed to add adc driver\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) module_init(adc_init);