Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  linux/arch/arm/mach-rpc/dma.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (C) 1998 Russell King
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  DMA functions specific to RiscPC architecture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/mman.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/fiq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <asm/mach/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <asm/hardware/iomd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) struct iomd_dma {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	struct dma_struct	dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	void __iomem		*base;		/* Controller base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	int			irq;		/* Controller IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	unsigned int		state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	dma_addr_t		cur_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	unsigned int		cur_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	dma_addr_t		dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	unsigned int		dma_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	dma_size_8	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	dma_size_16	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	dma_size_32	= 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	dma_size_128	= 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) } dma_size_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define TRANSFER_SIZE	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define CURA	(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define ENDA	(IOMD_IO0ENDA - IOMD_IO0CURA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define CURB	(IOMD_IO0CURB - IOMD_IO0CURA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define ENDB	(IOMD_IO0ENDB - IOMD_IO0CURA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define CR	(IOMD_IO0CR - IOMD_IO0CURA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define ST	(IOMD_IO0ST - IOMD_IO0CURA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static void iomd_get_next_sg(struct iomd_dma *idma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	unsigned long end, offset, flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	if (idma->dma.sg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		idma->cur_addr = idma->dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		offset = idma->cur_addr & ~PAGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		end = offset + idma->dma_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		if (end > PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 			end = PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		if (offset + TRANSFER_SIZE >= end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 			flags |= DMA_END_L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		idma->cur_len = end - TRANSFER_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		idma->dma_len -= end - offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		idma->dma_addr += end - offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		if (idma->dma_len == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 			if (idma->dma.sgcount > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 				idma->dma.sg = sg_next(idma->dma.sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 				idma->dma_addr = idma->dma.sg->dma_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 				idma->dma_len = idma->dma.sg->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 				idma->dma.sgcount--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 			} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 				idma->dma.sg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 				flags |= DMA_END_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		flags = DMA_END_S | DMA_END_L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		idma->cur_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		idma->cur_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	idma->cur_len |= flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) static irqreturn_t iomd_dma_handle(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	struct iomd_dma *idma = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	void __iomem *base = idma->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	unsigned int state = idma->state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	unsigned int status, cur, end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		status = readb(base + ST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		if (!(status & DMA_ST_INT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 			goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		if ((state ^ status) & DMA_ST_AB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 			iomd_get_next_sg(idma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		// This efficiently implements state = OFL != AB ? AB : 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		state = ((status >> 2) ^ status) & DMA_ST_AB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		if (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 			cur = CURA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 			end = ENDA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			cur = CURB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 			end = ENDB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		writel(idma->cur_addr, base + cur);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		writel(idma->cur_len, base + end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		if (status & DMA_ST_OFL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		    idma->cur_len == (DMA_END_S|DMA_END_L))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	} while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	state = ~DMA_ST_AB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	disable_irq_nosync(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	idma->state = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static int iomd_request_dma(unsigned int chan, dma_t *dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	return request_irq(idma->irq, iomd_dma_handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			   0, idma->dma.device_id, idma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static void iomd_free_dma(unsigned int chan, dma_t *dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	free_irq(idma->irq, idma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static struct device isa_dma_dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	.init_name		= "fallback device",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	.coherent_dma_mask	= ~(dma_addr_t)0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	.dma_mask		= &isa_dma_dev.coherent_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static void iomd_enable_dma(unsigned int chan, dma_t *dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	void __iomem *base = idma->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	unsigned int ctrl = TRANSFER_SIZE | DMA_CR_E;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	if (idma->dma.invalid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		idma->dma.invalid = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		 * Cope with ISA-style drivers which expect cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		 * coherence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		if (!idma->dma.sg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			idma->dma.sg = &idma->dma.buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			idma->dma.sgcount = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			idma->dma.buf.length = idma->dma.count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			idma->dma.buf.dma_address = dma_map_single(&isa_dma_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 				idma->dma.addr, idma->dma.count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 				idma->dma.dma_mode == DMA_MODE_READ ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 				DMA_FROM_DEVICE : DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		idma->dma_addr = idma->dma.sg->dma_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		idma->dma_len = idma->dma.sg->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		writeb(DMA_CR_C, base + CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		idma->state = DMA_ST_AB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	if (idma->dma.dma_mode == DMA_MODE_READ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		ctrl |= DMA_CR_D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	writeb(ctrl, base + CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	enable_irq(idma->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static void iomd_disable_dma(unsigned int chan, dma_t *dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	void __iomem *base = idma->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	if (idma->state != ~DMA_ST_AB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		disable_irq(idma->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	writeb(0, base + CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static int iomd_set_dma_speed(unsigned int chan, dma_t *dma, int cycle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	int tcr, speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	if (cycle < 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		speed = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	else if (cycle <= 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		speed = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	else if (cycle < 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		speed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		speed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	tcr = iomd_readb(IOMD_DMATCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	speed &= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	switch (chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	case DMA_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		tcr = (tcr & ~0x03) | speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	case DMA_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		tcr = (tcr & ~0x0c) | (speed << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	case DMA_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		tcr = (tcr & ~0x30) | (speed << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	case DMA_3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		tcr = (tcr & ~0xc0) | (speed << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	iomd_writeb(tcr, IOMD_DMATCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	return speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static struct dma_ops iomd_dma_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	.type		= "IOMD",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	.request	= iomd_request_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	.free		= iomd_free_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	.enable		= iomd_enable_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	.disable	= iomd_disable_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	.setspeed	= iomd_set_dma_speed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static struct fiq_handler fh = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	.name	= "floppydma"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct floppy_dma {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	struct dma_struct	dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	unsigned int		fiq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static void floppy_enable_dma(unsigned int chan, dma_t *dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	struct floppy_dma *fdma = container_of(dma, struct floppy_dma, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	void *fiqhandler_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	unsigned int fiqhandler_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	struct pt_regs regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	if (fdma->dma.sg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	if (fdma->dma.dma_mode == DMA_MODE_READ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		extern unsigned char floppy_fiqin_start, floppy_fiqin_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		fiqhandler_start = &floppy_fiqin_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		fiqhandler_length = &floppy_fiqin_end - &floppy_fiqin_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		extern unsigned char floppy_fiqout_start, floppy_fiqout_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		fiqhandler_start = &floppy_fiqout_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		fiqhandler_length = &floppy_fiqout_end - &floppy_fiqout_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	regs.ARM_r9  = fdma->dma.count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	regs.ARM_r10 = (unsigned long)fdma->dma.addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	regs.ARM_fp  = (unsigned long)FLOPPYDMA_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	if (claim_fiq(&fh)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		printk("floppydma: couldn't claim FIQ.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	set_fiq_handler(fiqhandler_start, fiqhandler_length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	set_fiq_regs(&regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	enable_fiq(fdma->fiq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static void floppy_disable_dma(unsigned int chan, dma_t *dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	struct floppy_dma *fdma = container_of(dma, struct floppy_dma, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	disable_fiq(fdma->fiq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	release_fiq(&fh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static int floppy_get_residue(unsigned int chan, dma_t *dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	struct pt_regs regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	get_fiq_regs(&regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	return regs.ARM_r9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static struct dma_ops floppy_dma_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	.type		= "FIQDMA",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	.enable		= floppy_enable_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	.disable	= floppy_disable_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	.residue	= floppy_get_residue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)  * This is virtual DMA - we don't need anything here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static void sound_enable_disable_dma(unsigned int chan, dma_t *dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static struct dma_ops sound_dma_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	.type		= "VIRTUAL",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	.enable		= sound_enable_disable_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	.disable	= sound_enable_disable_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static struct iomd_dma iomd_dma[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static struct floppy_dma floppy_dma = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	.dma		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		.d_ops	= &floppy_dma_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	.fiq		= FIQ_FLOPPYDATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static dma_t sound_dma = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	.d_ops		= &sound_dma_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static int __init rpc_dma_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	iomd_writeb(0, IOMD_IO0CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	iomd_writeb(0, IOMD_IO1CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	iomd_writeb(0, IOMD_IO2CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	iomd_writeb(0, IOMD_IO3CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	iomd_writeb(0xa0, IOMD_DMATCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	 * Setup DMA channels 2,3 to be for podules
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	 * and channels 0,1 for internal devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	iomd_writeb(DMA_EXT_IO3|DMA_EXT_IO2, IOMD_DMAEXT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	iomd_dma[DMA_0].base	= IOMD_BASE + IOMD_IO0CURA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	iomd_dma[DMA_0].irq	= IRQ_DMA0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	iomd_dma[DMA_1].base	= IOMD_BASE + IOMD_IO1CURA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	iomd_dma[DMA_1].irq	= IRQ_DMA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	iomd_dma[DMA_2].base	= IOMD_BASE + IOMD_IO2CURA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	iomd_dma[DMA_2].irq	= IRQ_DMA2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	iomd_dma[DMA_3].base	= IOMD_BASE + IOMD_IO3CURA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	iomd_dma[DMA_3].irq	= IRQ_DMA3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	iomd_dma[DMA_S0].base	= IOMD_BASE + IOMD_SD0CURA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	iomd_dma[DMA_S0].irq	= IRQ_DMAS0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	iomd_dma[DMA_S1].base	= IOMD_BASE + IOMD_SD1CURA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	iomd_dma[DMA_S1].irq	= IRQ_DMAS1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	for (i = DMA_0; i <= DMA_S1; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		iomd_dma[i].dma.d_ops = &iomd_dma_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		ret = isa_dma_add(i, &iomd_dma[i].dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 			printk("IOMDDMA%u: unable to register: %d\n", i, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	ret = isa_dma_add(DMA_VIRTUAL_FLOPPY, &floppy_dma.dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		printk("IOMDFLOPPY: unable to register: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	ret = isa_dma_add(DMA_VIRTUAL_SOUND, &sound_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		printk("IOMDSOUND: unable to register: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) core_initcall(rpc_dma_init);