Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Device Tree support for Rockchip SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (c) 2013 MundoReader S.L.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Author: Heiko Stuebner <heiko@sntech.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/hardware/cache-l2x0.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "pm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RK3288_TIMER6_7_PHYS 0xff810000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static void __init rockchip_timer_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	if (of_machine_is_compatible("rockchip,rk3288")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		 * Most/all uboot versions for rk3288 don't enable timer7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		 * which is needed for the architected timer to work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		 * So make sure it is running during early boot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		reg_base = ioremap(RK3288_TIMER6_7_PHYS, SZ_16K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		if (reg_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 			writel(0, reg_base + 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 			writel(0xffffffff, reg_base + 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 			writel(0xffffffff, reg_base + 0x24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 			writel(1, reg_base + 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 			dsb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 			iounmap(reg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 			pr_err("rockchip: could not map timer7 registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	of_clk_init(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	timer_probe();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static void __init rockchip_dt_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	rockchip_suspend_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static const char * const rockchip_board_dt_compat[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	"rockchip,rk2928",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	"rockchip,rk3066a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	"rockchip,rk3066b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	"rockchip,rk3188",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	"rockchip,rk3228",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	"rockchip,rk3288",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	"rockchip,rv1108",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) DT_MACHINE_START(ROCKCHIP_DT, "Rockchip (Device Tree)")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	.l2c_aux_val	= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	.l2c_aux_mask	= ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	.init_time	= rockchip_timer_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	.dt_compat	= rockchip_board_dt_compat,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	.init_machine	= rockchip_dt_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MACHINE_END