^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Tony Xie <tony.xie@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef __MACH_ROCKCHIP_PM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define __MACH_ROCKCHIP_PM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) extern unsigned long rkpm_bootdata_cpusp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) extern unsigned long rkpm_bootdata_cpu_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) extern unsigned long rkpm_bootdata_l2ctlr_f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) extern unsigned long rkpm_bootdata_l2ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) extern unsigned long rkpm_bootdata_ddr_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) extern unsigned long rkpm_bootdata_ddr_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) extern unsigned long rk3288_bootram_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) void rockchip_slp_cpu_resume(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) void __init rockchip_suspend_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static inline void rockchip_suspend_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /****** following is rk3288 defined **********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RK3288_PMU_WAKEUP_CFG0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RK3288_PMU_WAKEUP_CFG1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RK3288_PMU_PWRMODE_CON 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RK3288_PMU_OSC_CNT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RK3288_PMU_PLL_CNT 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RK3288_PMU_STABL_CNT 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RK3288_PMU_DDR0IO_PWRON_CNT 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RK3288_PMU_DDR1IO_PWRON_CNT 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RK3288_PMU_CORE_PWRDWN_CNT 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RK3288_PMU_CORE_PWRUP_CNT 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RK3288_PMU_GPU_PWRDWN_CNT 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RK3288_PMU_GPU_PWRUP_CNT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RK3288_PMU_WAKEUP_RST_CLR_CNT 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RK3288_PMU_PWRMODE_CON1 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RK3288_SGRF_SOC_CON0 (0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RK3288_SGRF_FAST_BOOT_ADDR (0x0120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SGRF_PCLK_WDT_GATE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SGRF_PCLK_WDT_GATE_WRITE BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SGRF_FAST_BOOT_EN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SGRF_FAST_BOOT_EN_WRITE BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RK3288_SGRF_CPU_CON0 (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SGRF_DAPDEVICEEN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SGRF_DAPDEVICEEN_WRITE BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* PMU_WAKEUP_CFG1 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PMU_ARMINT_WAKEUP_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PMU_GPIOINT_WAKEUP_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) enum rk3288_pwr_mode_con {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) PMU_PWR_MODE_EN = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) PMU_CLK_CORE_SRC_GATE_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) PMU_GLOBAL_INT_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PMU_L2FLUSH_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) PMU_BUS_PD_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) PMU_A12_0_PD_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) PMU_SCU_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) PMU_PLL_PD_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) PMU_CHIP_PD_EN, /* POWER OFF PIN ENABLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) PMU_PWROFF_COMB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) PMU_ALIVE_USE_LF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) PMU_PMU_USE_LF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) PMU_OSC_24M_DIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) PMU_INPUT_CLAMP_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) PMU_WAKEUP_RESET_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) PMU_SREF0_ENTER_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) PMU_SREF1_ENTER_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) PMU_DDR0IO_RET_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) PMU_DDR1IO_RET_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) PMU_DDR0_GATING_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) PMU_DDR1_GATING_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) PMU_DDR0IO_RET_DE_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) PMU_DDR1IO_RET_DE_REQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) enum rk3288_pwr_mode_con1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) PMU_CLR_BUS = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) PMU_CLR_CORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) PMU_CLR_CPUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) PMU_CLR_ALIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) PMU_CLR_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) PMU_CLR_PERI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) PMU_CLR_GPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) PMU_CLR_VIDEO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) PMU_CLR_HEVC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) PMU_CLR_VIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #endif /* __MACH_ROCKCHIP_PM_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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