Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: Tony Xie <tony.xie@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <asm/tlbflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <asm/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include "pm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) /* These enum are option of low power mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	ROCKCHIP_ARM_OFF_LOGIC_NORMAL = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	ROCKCHIP_ARM_OFF_LOGIC_DEEP = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) struct rockchip_pm_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	const struct platform_suspend_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	int (*init)(struct device_node *np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) static void __iomem *rk3288_bootram_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) static phys_addr_t rk3288_bootram_phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static struct regmap *pmu_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) static struct regmap *sgrf_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) static struct regmap *grf_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) static u32 rk3288_pmu_pwr_mode_con;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) static u32 rk3288_sgrf_soc_con0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) static u32 rk3288_sgrf_cpu_con0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) static inline u32 rk3288_l2_config(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	u32 l2ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (l2ctlr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	return l2ctlr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) static void __init rk3288_config_bootdata(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	rkpm_bootdata_cpusp = rk3288_bootram_phy + (SZ_4K - 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	rkpm_bootdata_cpu_code = __pa_symbol(cpu_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	rkpm_bootdata_l2ctlr_f  = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	rkpm_bootdata_l2ctlr = rk3288_l2_config();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define GRF_UOC0_CON0			0x320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define GRF_UOC1_CON0			0x334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define GRF_UOC2_CON0			0x348
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define GRF_SIDDQ			BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static bool rk3288_slp_disable_osc(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	static const u32 reg_offset[] = { GRF_UOC0_CON0, GRF_UOC1_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 					  GRF_UOC2_CON0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	u32 reg, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	 * if any usb phy is still on(GRF_SIDDQ==0), that means we need the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	 * function of usb wakeup, so do not switch to 32khz, since the usb phy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	 * clk does not connect to 32khz osc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	for (i = 0; i < ARRAY_SIZE(reg_offset); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		regmap_read(grf_regmap, reg_offset[i], &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		if (!(reg & GRF_SIDDQ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 			return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) static void rk3288_slp_mode_set(int level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	u32 mode_set, mode_set1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	bool osc_disable = rk3288_slp_disable_osc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	regmap_read(sgrf_regmap, RK3288_SGRF_CPU_CON0, &rk3288_sgrf_cpu_con0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	regmap_read(sgrf_regmap, RK3288_SGRF_SOC_CON0, &rk3288_sgrf_soc_con0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	regmap_read(pmu_regmap, RK3288_PMU_PWRMODE_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		    &rk3288_pmu_pwr_mode_con);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	 * SGRF_FAST_BOOT_EN - system to boot from FAST_BOOT_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	 * PCLK_WDT_GATE - disable WDT during suspend.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		     SGRF_PCLK_WDT_GATE | SGRF_FAST_BOOT_EN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		     | SGRF_PCLK_WDT_GATE_WRITE | SGRF_FAST_BOOT_EN_WRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	 * The dapswjdp can not auto reset before resume, that cause it may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	 * access some illegal address during resume. Let's disable it before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	 * suspend, and the MASKROM will enable it back.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	regmap_write(sgrf_regmap, RK3288_SGRF_CPU_CON0, SGRF_DAPDEVICEEN_WRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	/* booting address of resuming system is from this register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	regmap_write(sgrf_regmap, RK3288_SGRF_FAST_BOOT_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		     rk3288_bootram_phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	mode_set = BIT(PMU_GLOBAL_INT_DISABLE) | BIT(PMU_L2FLUSH_EN) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		   BIT(PMU_SREF0_ENTER_EN) | BIT(PMU_SREF1_ENTER_EN) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		   BIT(PMU_DDR0_GATING_EN) | BIT(PMU_DDR1_GATING_EN) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		   BIT(PMU_PWR_MODE_EN) | BIT(PMU_CHIP_PD_EN) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		   BIT(PMU_SCU_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	mode_set1 = BIT(PMU_CLR_CORE) | BIT(PMU_CLR_CPUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	if (level == ROCKCHIP_ARM_OFF_LOGIC_DEEP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		/* arm off, logic deep sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		mode_set |= BIT(PMU_BUS_PD_EN) | BIT(PMU_PMU_USE_LF) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			    BIT(PMU_DDR1IO_RET_EN) | BIT(PMU_DDR0IO_RET_EN) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			    BIT(PMU_ALIVE_USE_LF) | BIT(PMU_PLL_PD_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		if (osc_disable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			mode_set |= BIT(PMU_OSC_24M_DIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		mode_set1 |= BIT(PMU_CLR_ALIVE) | BIT(PMU_CLR_BUS) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			     BIT(PMU_CLR_PERI) | BIT(PMU_CLR_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		regmap_write(pmu_regmap, RK3288_PMU_WAKEUP_CFG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 			     PMU_ARMINT_WAKEUP_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		 * In deep suspend we use PMU_PMU_USE_LF to let the rk3288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		 * switch its main clock supply to the alternative 32kHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		 * source. Therefore set 30ms on a 32kHz clock for pmic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		 * stabilization. Similar 30ms on 24MHz for the other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		 * mode below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, 32 * 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		/* only wait for stabilization, if we turned the osc off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 					 osc_disable ? 32 * 30 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		 * arm off, logic normal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		 * if pmu_clk_core_src_gate_en is not set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		 * wakeup will be error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		mode_set |= BIT(PMU_CLK_CORE_SRC_GATE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		regmap_write(pmu_regmap, RK3288_PMU_WAKEUP_CFG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			     PMU_ARMINT_WAKEUP_EN | PMU_GPIOINT_WAKEUP_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		/* 30ms on a 24MHz clock for pmic stabilization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		regmap_write(pmu_regmap, RK3288_PMU_STABL_CNT, 24000 * 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		/* oscillator is still running, so no need to wait */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		regmap_write(pmu_regmap, RK3288_PMU_OSC_CNT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON, mode_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON1, mode_set1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static void rk3288_slp_mode_set_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	regmap_write(sgrf_regmap, RK3288_SGRF_CPU_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		     rk3288_sgrf_cpu_con0 | SGRF_DAPDEVICEEN_WRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	regmap_write(pmu_regmap, RK3288_PMU_PWRMODE_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		     rk3288_pmu_pwr_mode_con);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		     rk3288_sgrf_soc_con0 | SGRF_PCLK_WDT_GATE_WRITE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		     | SGRF_FAST_BOOT_EN_WRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static int rockchip_lpmode_enter(unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	flush_cache_all();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	cpu_do_idle();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	pr_err("%s: Failed to suspend\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static int rk3288_suspend_enter(suspend_state_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	local_fiq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	rk3288_slp_mode_set(ROCKCHIP_ARM_OFF_LOGIC_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	cpu_suspend(0, rockchip_lpmode_enter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	rk3288_slp_mode_set_resume();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	local_fiq_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static int rk3288_suspend_prepare(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	return regulator_suspend_prepare(PM_SUSPEND_MEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static void rk3288_suspend_finish(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	if (regulator_suspend_finish())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		pr_err("%s: Suspend finish failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static int __init rk3288_suspend_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	struct device_node *sram_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	pmu_regmap = syscon_node_to_regmap(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	if (IS_ERR(pmu_regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		pr_err("%s: could not find pmu regmap\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		return PTR_ERR(pmu_regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	sgrf_regmap = syscon_regmap_lookup_by_compatible(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 				"rockchip,rk3288-sgrf");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	if (IS_ERR(sgrf_regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		pr_err("%s: could not find sgrf regmap\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		return PTR_ERR(sgrf_regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	grf_regmap = syscon_regmap_lookup_by_compatible(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 				"rockchip,rk3288-grf");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	if (IS_ERR(grf_regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		pr_err("%s: could not find grf regmap\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		return PTR_ERR(grf_regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	sram_np = of_find_compatible_node(NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 					  "rockchip,rk3288-pmu-sram");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	if (!sram_np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		pr_err("%s: could not find bootram dt node\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	rk3288_bootram_base = of_iomap(sram_np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	if (!rk3288_bootram_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		pr_err("%s: could not map bootram base\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		of_node_put(sram_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	ret = of_address_to_resource(sram_np, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		pr_err("%s: could not get bootram phy addr\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		of_node_put(sram_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	rk3288_bootram_phy = res.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	of_node_put(sram_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	rk3288_config_bootdata();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	/* copy resume code and data to bootsram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	memcpy(rk3288_bootram_base, rockchip_slp_cpu_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	       rk3288_bootram_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static const struct platform_suspend_ops rk3288_suspend_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	.enter   = rk3288_suspend_enter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	.valid   = suspend_valid_only_mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	.prepare = rk3288_suspend_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	.finish  = rk3288_suspend_finish,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static const struct rockchip_pm_data rk3288_pm_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	.ops = &rk3288_suspend_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	.init = rk3288_suspend_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static const struct of_device_id rockchip_pmu_of_device_ids[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		.compatible = "rockchip,rk3288-pmu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		.data = &rk3288_pm_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	{ /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) void __init rockchip_suspend_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	const struct rockchip_pm_data *pm_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	np = of_find_matching_node_and_match(NULL, rockchip_pmu_of_device_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 					     &match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	if (!match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		pr_err("Failed to find PMU node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	pm_data = (struct rockchip_pm_data *) match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	if (pm_data->init) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		ret = pm_data->init(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 			pr_err("%s: matches init error %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 			return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	suspend_set_ops(pm_data->ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }