^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2002 ARM Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2014 The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/qcom_scm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/smp_plat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define VDD_SC1_ARRAY_CLAMP_GFS_CTL 0x35a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SCSS_CPU1CORE_RESET 0x2d80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SCSS_DBG_STATUS_CORE_PWRDUP 0x2e64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define APCS_CPU_PWR_CTL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PLL_CLAMP BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CORE_PWRD_UP BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define COREPOR_RST BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CORE_RST BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define L2DT_SLP BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CLAMP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define APC_PWR_GATE_CTL 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define BHS_CNT_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LDO_PWR_DWN_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define LDO_BYP_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define BHS_SEG_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define BHS_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define APCS_SAW2_VCTL 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define APCS_SAW2_2_VCTL 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) extern void secondary_startup_arm(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #ifdef CONFIG_HOTPLUG_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static void qcom_cpu_die(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) wfi();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static int scss_release_secondary(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct device_node *node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) node = of_find_compatible_node(NULL, NULL, "qcom,gcc-msm8660");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (!node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) pr_err("%s: can't find node\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) of_node_put(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (!base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) writel_relaxed(0, base + VDD_SC1_ARRAY_CLAMP_GFS_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) writel_relaxed(0, base + SCSS_CPU1CORE_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) writel_relaxed(3, base + SCSS_DBG_STATUS_CORE_PWRDUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) iounmap(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static int kpssv1_release_secondary(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) void __iomem *reg, *saw_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct device_node *cpu_node, *acc_node, *saw_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) cpu_node = of_get_cpu_node(cpu, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (!cpu_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) acc_node = of_parse_phandle(cpu_node, "qcom,acc", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (!acc_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) goto out_acc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (!saw_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) goto out_saw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) reg = of_iomap(acc_node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if (!reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) goto out_acc_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) saw_reg = of_iomap(saw_node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (!saw_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) goto out_saw_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Turn on CPU rail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) writel_relaxed(0xA4, saw_reg + APCS_SAW2_VCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) udelay(512);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Krait bring-up sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) val = PLL_CLAMP | L2DT_SLP | CLAMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) val &= ~L2DT_SLP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ndelay(300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) val |= COREPOR_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) val &= ~CLAMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) val &= ~COREPOR_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) val |= CORE_PWRD_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) iounmap(saw_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) out_saw_map:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) iounmap(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) out_acc_map:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) of_node_put(saw_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) out_saw:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) of_node_put(acc_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) out_acc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) of_node_put(cpu_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static int kpssv2_release_secondary(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct device_node *cpu_node, *l2_node, *acc_node, *saw_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) void __iomem *l2_saw_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) cpu_node = of_get_cpu_node(cpu, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (!cpu_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) acc_node = of_parse_phandle(cpu_node, "qcom,acc", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (!acc_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) goto out_acc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) l2_node = of_parse_phandle(cpu_node, "next-level-cache", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (!l2_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) goto out_l2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) saw_node = of_parse_phandle(l2_node, "qcom,saw", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (!saw_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) goto out_saw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) reg = of_iomap(acc_node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (!reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) goto out_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) l2_saw_base = of_iomap(saw_node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (!l2_saw_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) goto out_saw_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* Turn on the BHS, turn off LDO Bypass and power down LDO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) reg_val = (64 << BHS_CNT_SHIFT) | (0x3f << LDO_PWR_DWN_SHIFT) | BHS_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* wait for the BHS to settle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Turn on BHS segments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) reg_val |= 0x3f << BHS_SEG_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* wait for the BHS to settle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* Finally turn on the bypass so that BHS supplies power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) reg_val |= 0x3f << LDO_BYP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* enable max phases */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) writel_relaxed(0x10003, l2_saw_base + APCS_SAW2_2_VCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) reg_val = COREPOR_RST | CLAMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) reg_val &= ~CLAMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) reg_val &= ~COREPOR_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) reg_val |= CORE_PWRD_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) iounmap(l2_saw_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) out_saw_map:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) iounmap(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) out_map:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) of_node_put(saw_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) out_saw:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) of_node_put(l2_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) out_l2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) of_node_put(acc_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) out_acc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) of_node_put(cpu_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static DEFINE_PER_CPU(int, cold_boot_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static int qcom_boot_secondary(unsigned int cpu, int (*func)(unsigned int))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (!per_cpu(cold_boot_done, cpu)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ret = func(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) per_cpu(cold_boot_done, cpu) = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * Send the secondary CPU a soft interrupt, thereby causing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * the boot monitor to read the system wide flags register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * and branch to the address found there.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) arch_send_wakeup_ipi_mask(cpumask_of(cpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static int msm8660_boot_secondary(unsigned int cpu, struct task_struct *idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return qcom_boot_secondary(cpu, scss_release_secondary);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static int kpssv1_boot_secondary(unsigned int cpu, struct task_struct *idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return qcom_boot_secondary(cpu, kpssv1_release_secondary);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static int kpssv2_boot_secondary(unsigned int cpu, struct task_struct *idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return qcom_boot_secondary(cpu, kpssv2_release_secondary);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static void __init qcom_smp_prepare_cpus(unsigned int max_cpus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (qcom_scm_set_cold_boot_addr(secondary_startup_arm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) cpu_present_mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) for_each_present_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (cpu == smp_processor_id())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) set_cpu_present(cpu, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) pr_warn("Failed to set CPU boot address, disabling SMP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static const struct smp_operations smp_msm8660_ops __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .smp_prepare_cpus = qcom_smp_prepare_cpus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .smp_boot_secondary = msm8660_boot_secondary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #ifdef CONFIG_HOTPLUG_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .cpu_die = qcom_cpu_die,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) CPU_METHOD_OF_DECLARE(qcom_smp, "qcom,gcc-msm8660", &smp_msm8660_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static const struct smp_operations qcom_smp_kpssv1_ops __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .smp_prepare_cpus = qcom_smp_prepare_cpus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .smp_boot_secondary = kpssv1_boot_secondary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #ifdef CONFIG_HOTPLUG_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .cpu_die = qcom_cpu_die,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) CPU_METHOD_OF_DECLARE(qcom_smp_kpssv1, "qcom,kpss-acc-v1", &qcom_smp_kpssv1_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static const struct smp_operations qcom_smp_kpssv2_ops __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .smp_prepare_cpus = qcom_smp_prepare_cpus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .smp_boot_secondary = kpssv2_boot_secondary,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #ifdef CONFIG_HOTPLUG_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .cpu_die = qcom_cpu_die,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) CPU_METHOD_OF_DECLARE(qcom_smp_kpssv2, "qcom,kpss-acc-v2", &qcom_smp_kpssv2_ops);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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