Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *  arch/arm/mach-pxa/include/mach/zeus.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *  Author:	David Vrabel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *  Created:	Sept 28, 2005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *  Copyright:	Arcom Control Systems Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  *  Maintained by: Marc Zyngier <maz@misterjones.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef _MACH_ZEUS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define _MACH_ZEUS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define ZEUS_NR_IRQS		(IRQ_BOARD_START + 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* Physical addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ZEUS_FLASH_PHYS		PXA_CS0_PHYS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ZEUS_ETH0_PHYS		PXA_CS1_PHYS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ZEUS_ETH1_PHYS		PXA_CS2_PHYS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ZEUS_CPLD_PHYS		(PXA_CS4_PHYS+0x2000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ZEUS_SRAM_PHYS		PXA_CS5_PHYS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ZEUS_PC104IO_PHYS	(0x30000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ZEUS_CPLD_VERSION_PHYS	(ZEUS_CPLD_PHYS + 0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ZEUS_CPLD_ISA_IRQ_PHYS	(ZEUS_CPLD_PHYS + 0x00800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ZEUS_CPLD_CONTROL_PHYS	(ZEUS_CPLD_PHYS + 0x01000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ZEUS_CPLD_EXTWDOG_PHYS	(ZEUS_CPLD_PHYS + 0x01800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* GPIOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ZEUS_AC97_GPIO		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ZEUS_WAKEUP_GPIO	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ZEUS_UARTA_GPIO		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ZEUS_UARTB_GPIO		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ZEUS_UARTC_GPIO		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ZEUS_UARTD_GPIO		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ZEUS_ETH0_GPIO		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ZEUS_ISA_GPIO		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ZEUS_BKLEN_GPIO		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ZEUS_USB2_PWREN_GPIO	22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ZEUS_PTT_GPIO		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ZEUS_CF_CD_GPIO         35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ZEUS_MMC_WP_GPIO        52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ZEUS_MMC_CD_GPIO        53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ZEUS_EXTGPIO_GPIO	91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ZEUS_CF_PWEN_GPIO       97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ZEUS_CF_RDY_GPIO        99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ZEUS_LCD_EN_GPIO	101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ZEUS_ETH1_GPIO		113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ZEUS_CAN_GPIO		116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ZEUS_EXT0_GPIO_BASE	128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ZEUS_EXT1_GPIO_BASE	160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ZEUS_USER_GPIO_BASE	192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ZEUS_EXT0_GPIO(x)	(ZEUS_EXT0_GPIO_BASE + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ZEUS_EXT1_GPIO(x)	(ZEUS_EXT1_GPIO_BASE + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ZEUS_USER_GPIO(x)	(ZEUS_USER_GPIO_BASE + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define	ZEUS_CAN_SHDN_GPIO	ZEUS_EXT1_GPIO(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)  * CPLD registers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)  * Only 4 registers, but spread over a 32MB address space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)  * Be gentle, and remap that over 32kB...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ZEUS_CPLD		IOMEM(0xf0000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ZEUS_CPLD_VERSION	(ZEUS_CPLD + 0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ZEUS_CPLD_ISA_IRQ	(ZEUS_CPLD + 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ZEUS_CPLD_CONTROL	(ZEUS_CPLD + 0x2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* CPLD register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ZEUS_CPLD_CONTROL_CF_RST        0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ZEUS_PC104IO		IOMEM(0xf1000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ZEUS_SRAM_SIZE		(256 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)