^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Support for the Arcom ZEUS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2006 Arcom Control Systems Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Loosely based on Arcom's 2.6.16.28.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Maintained by Marc Zyngier <maz@misterjones.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/leds.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/property.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/gpio/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/serial_8250.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/dm9000.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mmc/host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/spi/pxa2xx_spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/mtd/partitions.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/mtd/physmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/platform_data/i2c-pxa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/platform_data/pca953x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/apm-emulation.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/regulator/fixed.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <asm/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <asm/system_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include "pxa27x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include "devices.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <mach/regs-uart.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/platform_data/usb-ohci-pxa27x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/platform_data/mmc-pxamci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include "pxa27x-udc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include "udc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <linux/platform_data/video-pxafb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include "pm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <mach/audio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <linux/platform_data/pcmcia-pxa2xx_viper.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include "zeus.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <mach/smemc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include "generic.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * Interrupt handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static unsigned long zeus_irq_enabled_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static const int zeus_isa_irqs[] = { 3, 4, 5, 6, 7, 10, 11, 12, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static const int zeus_isa_irq_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 0, /* ISA irq #0, invalid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 0, /* ISA irq #1, invalid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 0, /* ISA irq #2, invalid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 1 << 0, /* ISA irq #3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 1 << 1, /* ISA irq #4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 1 << 2, /* ISA irq #5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 1 << 3, /* ISA irq #6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 1 << 4, /* ISA irq #7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 0, /* ISA irq #8, invalid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 0, /* ISA irq #9, invalid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 1 << 5, /* ISA irq #10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 1 << 6, /* ISA irq #11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 1 << 7, /* ISA irq #12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static inline int zeus_irq_to_bitmask(unsigned int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return zeus_isa_irq_map[irq - PXA_ISA_IRQ(0)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static inline int zeus_bit_to_irq(int bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return zeus_isa_irqs[bit] + PXA_ISA_IRQ(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static void zeus_ack_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) __raw_writew(zeus_irq_to_bitmask(d->irq), ZEUS_CPLD_ISA_IRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static void zeus_mask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) zeus_irq_enabled_mask &= ~(zeus_irq_to_bitmask(d->irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static void zeus_unmask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) zeus_irq_enabled_mask |= zeus_irq_to_bitmask(d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static inline unsigned long zeus_irq_pending(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return __raw_readw(ZEUS_CPLD_ISA_IRQ) & zeus_irq_enabled_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static void zeus_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned long pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) pending = zeus_irq_pending();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* we're in a chained irq handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * so ack the interrupt by hand */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) desc->irq_data.chip->irq_ack(&desc->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (likely(pending)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) irq = zeus_bit_to_irq(__ffs(pending));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) generic_handle_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) pending = zeus_irq_pending();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) } while (pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static struct irq_chip zeus_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .name = "ISA",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .irq_ack = zeus_ack_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .irq_mask = zeus_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .irq_unmask = zeus_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static void __init zeus_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int isa_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) pxa27x_init_irq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Peripheral IRQs. It would be nice to move those inside driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) configuration, but it is not supported at the moment. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) irq_set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO), IRQ_TYPE_EDGE_RISING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) irq_set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO), IRQ_TYPE_EDGE_RISING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) irq_set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO), IRQ_TYPE_EDGE_RISING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) irq_set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) IRQ_TYPE_EDGE_FALLING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) irq_set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO), IRQ_TYPE_EDGE_FALLING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* Setup ISA IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) for (level = 0; level < ARRAY_SIZE(zeus_isa_irqs); level++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) isa_irq = zeus_bit_to_irq(level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) irq_set_chip_and_handler(isa_irq, &zeus_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) irq_clear_status_flags(isa_irq, IRQ_NOREQUEST | IRQ_NOPROBE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) irq_set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) irq_set_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * Platform devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static struct resource zeus_mtd_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) [0] = { /* NOR Flash (up to 64MB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .start = ZEUS_FLASH_PHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .end = ZEUS_FLASH_PHYS + SZ_64M - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) [1] = { /* SRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .start = ZEUS_SRAM_PHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .end = ZEUS_SRAM_PHYS + SZ_512K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static struct physmap_flash_data zeus_flash_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .parts = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .nr_parts = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static struct platform_device zeus_mtd_devices[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .name = "physmap-flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .platform_data = &zeus_flash_data[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .resource = &zeus_mtd_resources[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .num_resources = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* Serial */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static struct resource zeus_serial_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .start = 0x10000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .end = 0x1000000f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .start = 0x10800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .end = 0x1080000f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .start = 0x11000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .end = 0x1100000f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .start = 0x40100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .end = 0x4010001f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .start = 0x40200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .end = 0x4020001f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .start = 0x40700000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .end = 0x4070001f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static struct plat_serial8250_port serial_platform_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* External UARTs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* FIXME: Shared IRQs on COM1-COM4 will not work properly on v1i1 hardware. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { /* COM1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .mapbase = 0x10000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .irq = PXA_GPIO_TO_IRQ(ZEUS_UARTA_GPIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .irqflags = IRQF_TRIGGER_RISING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .uartclk = 14745600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .regshift = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .iotype = UPIO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) { /* COM2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .mapbase = 0x10800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .irq = PXA_GPIO_TO_IRQ(ZEUS_UARTB_GPIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .irqflags = IRQF_TRIGGER_RISING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .uartclk = 14745600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .regshift = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .iotype = UPIO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) { /* COM3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .mapbase = 0x11000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .irq = PXA_GPIO_TO_IRQ(ZEUS_UARTC_GPIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .irqflags = IRQF_TRIGGER_RISING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .uartclk = 14745600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .regshift = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .iotype = UPIO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) { /* COM4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .mapbase = 0x11800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .irq = PXA_GPIO_TO_IRQ(ZEUS_UARTD_GPIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .irqflags = IRQF_TRIGGER_RISING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .uartclk = 14745600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .regshift = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .iotype = UPIO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* Internal UARTs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) { /* FFUART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .membase = (void *)&FFUART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .mapbase = __PREG(FFUART),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .irq = IRQ_FFUART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .uartclk = 921600 * 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .regshift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .iotype = UPIO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) { /* BTUART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .membase = (void *)&BTUART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .mapbase = __PREG(BTUART),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .irq = IRQ_BTUART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .uartclk = 921600 * 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .regshift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .iotype = UPIO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) { /* STUART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .membase = (void *)&STUART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .mapbase = __PREG(STUART),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .irq = IRQ_STUART,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .uartclk = 921600 * 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .regshift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .iotype = UPIO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static struct platform_device zeus_serial_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .name = "serial8250",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .id = PLAT8250_DEV_PLATFORM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .platform_data = serial_platform_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .num_resources = ARRAY_SIZE(zeus_serial_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .resource = zeus_serial_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* Ethernet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static struct resource zeus_dm9k0_resource[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .start = ZEUS_ETH0_PHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .end = ZEUS_ETH0_PHYS + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .flags = IORESOURCE_MEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .start = ZEUS_ETH0_PHYS + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .end = ZEUS_ETH0_PHYS + 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .flags = IORESOURCE_MEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .start = PXA_GPIO_TO_IRQ(ZEUS_ETH0_GPIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .end = PXA_GPIO_TO_IRQ(ZEUS_ETH0_GPIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static struct resource zeus_dm9k1_resource[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .start = ZEUS_ETH1_PHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .end = ZEUS_ETH1_PHYS + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .flags = IORESOURCE_MEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .start = ZEUS_ETH1_PHYS + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .end = ZEUS_ETH1_PHYS + 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .start = PXA_GPIO_TO_IRQ(ZEUS_ETH1_GPIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .end = PXA_GPIO_TO_IRQ(ZEUS_ETH1_GPIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static struct dm9000_plat_data zeus_dm9k_platdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .flags = DM9000_PLATF_16BITONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static struct platform_device zeus_dm9k0_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .name = "dm9000",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .num_resources = ARRAY_SIZE(zeus_dm9k0_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .resource = zeus_dm9k0_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .platform_data = &zeus_dm9k_platdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static struct platform_device zeus_dm9k1_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .name = "dm9000",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .num_resources = ARRAY_SIZE(zeus_dm9k1_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .resource = zeus_dm9k1_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .platform_data = &zeus_dm9k_platdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* External SRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static struct resource zeus_sram_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .start = ZEUS_SRAM_PHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .end = ZEUS_SRAM_PHYS + ZEUS_SRAM_SIZE * 2 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static struct platform_device zeus_sram_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .name = "pxa2xx-8bit-sram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .num_resources = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .resource = &zeus_sram_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* SPI interface on SSP3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static struct pxa2xx_spi_controller pxa2xx_spi_ssp3_master_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .num_chipselect = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .enable_dma = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* CAN bus on SPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static struct regulator_consumer_supply can_regulator_consumer =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) REGULATOR_SUPPLY("vdd", "spi3.0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static struct regulator_init_data can_regulator_init_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .constraints = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .valid_ops_mask = REGULATOR_CHANGE_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .consumer_supplies = &can_regulator_consumer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .num_consumer_supplies = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static struct fixed_voltage_config can_regulator_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .supply_name = "CAN_SHDN",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .microvolts = 3300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .init_data = &can_regulator_init_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static struct platform_device can_regulator_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .name = "reg-fixed-voltage",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .platform_data = &can_regulator_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static struct gpiod_lookup_table can_regulator_gpiod_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .dev_id = "reg-fixed-voltage.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) GPIO_LOOKUP("gpio-pxa", ZEUS_CAN_SHDN_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) NULL, GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static const struct property_entry mcp251x_properties[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) PROPERTY_ENTRY_U32("clock-frequency", 16000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static struct spi_board_info zeus_spi_board_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .modalias = "mcp2515",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .properties = mcp251x_properties,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .irq = PXA_GPIO_TO_IRQ(ZEUS_CAN_GPIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .max_speed_hz = 1*1000*1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .bus_num = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .mode = SPI_MODE_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .chip_select = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* Leds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static struct gpio_led zeus_leds[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .name = "zeus:yellow:1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .default_trigger = "heartbeat",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .gpio = ZEUS_EXT0_GPIO(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .active_low = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .name = "zeus:yellow:2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .default_trigger = "default-on",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .gpio = ZEUS_EXT0_GPIO(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .active_low = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .name = "zeus:yellow:3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .default_trigger = "default-on",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .gpio = ZEUS_EXT0_GPIO(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .active_low = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static struct gpio_led_platform_data zeus_leds_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .leds = zeus_leds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .num_leds = ARRAY_SIZE(zeus_leds),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static struct platform_device zeus_leds_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .name = "leds-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .platform_data = &zeus_leds_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static void zeus_cf_reset(int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) u16 cpld_state = __raw_readw(ZEUS_CPLD_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) cpld_state |= ZEUS_CPLD_CONTROL_CF_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) cpld_state &= ~ZEUS_CPLD_CONTROL_CF_RST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) __raw_writew(cpld_state, ZEUS_CPLD_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static struct arcom_pcmcia_pdata zeus_pcmcia_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .cd_gpio = ZEUS_CF_CD_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .rdy_gpio = ZEUS_CF_RDY_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .pwr_gpio = ZEUS_CF_PWEN_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .reset = zeus_cf_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static struct platform_device zeus_pcmcia_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .name = "zeus-pcmcia",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .platform_data = &zeus_pcmcia_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static struct resource zeus_max6369_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .start = ZEUS_CPLD_EXTWDOG_PHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .end = ZEUS_CPLD_EXTWDOG_PHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct platform_device zeus_max6369_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .name = "max6369_wdt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .resource = &zeus_max6369_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .num_resources = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* AC'97 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static pxa2xx_audio_ops_t zeus_ac97_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .reset_gpio = 95,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * USB host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static struct regulator_consumer_supply zeus_ohci_regulator_supplies[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) REGULATOR_SUPPLY("vbus2", "pxa27x-ohci"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static struct regulator_init_data zeus_ohci_regulator_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .constraints = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .valid_ops_mask = REGULATOR_CHANGE_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .num_consumer_supplies = ARRAY_SIZE(zeus_ohci_regulator_supplies),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .consumer_supplies = zeus_ohci_regulator_supplies,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static struct fixed_voltage_config zeus_ohci_regulator_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .supply_name = "vbus2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .microvolts = 5000000, /* 5.0V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .startup_delay = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .init_data = &zeus_ohci_regulator_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static struct platform_device zeus_ohci_regulator_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .name = "reg-fixed-voltage",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .platform_data = &zeus_ohci_regulator_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static struct gpiod_lookup_table zeus_ohci_regulator_gpiod_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .dev_id = "reg-fixed-voltage.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) GPIO_LOOKUP("gpio-pxa", ZEUS_USB2_PWREN_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) NULL, GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static struct pxaohci_platform_data zeus_ohci_platform_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .port_mode = PMM_NPS_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* Clear Power Control Polarity Low and set Power Sense
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * Polarity Low. Supply power to USB ports. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .flags = ENABLE_PORT_ALL | POWER_SENSE_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static void __init zeus_register_ohci(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) /* Port 2 is shared between host and client interface. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) pxa_set_ohci_info(&zeus_ohci_platform_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) * Flat Panel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static void zeus_lcd_power(int on, struct fb_var_screeninfo *si)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) gpio_set_value(ZEUS_LCD_EN_GPIO, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static void zeus_backlight_power(int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) gpio_set_value(ZEUS_BKLEN_GPIO, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static int zeus_setup_fb_gpios(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if ((err = gpio_request(ZEUS_LCD_EN_GPIO, "LCD_EN")))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if ((err = gpio_direction_output(ZEUS_LCD_EN_GPIO, 0)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) goto out_err_lcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if ((err = gpio_request(ZEUS_BKLEN_GPIO, "BKLEN")))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) goto out_err_lcd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if ((err = gpio_direction_output(ZEUS_BKLEN_GPIO, 0)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) goto out_err_bkl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) out_err_bkl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) gpio_free(ZEUS_BKLEN_GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) out_err_lcd:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) gpio_free(ZEUS_LCD_EN_GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) out_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static struct pxafb_mode_info zeus_fb_mode_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .pixclock = 39722,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .xres = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .yres = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .bpp = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .hsync_len = 63,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .left_margin = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .right_margin = 81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .vsync_len = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .upper_margin = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .lower_margin = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .sync = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static struct pxafb_mach_info zeus_fb_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .modes = zeus_fb_mode_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .num_modes = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .pxafb_lcd_power = zeus_lcd_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .pxafb_backlight_power = zeus_backlight_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * MMC/SD Device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * The card detect interrupt isn't debounced so we delay it by 250ms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * to give the card a chance to fully insert/eject.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static struct pxamci_platform_data zeus_mci_platform_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .detect_delay_ms = 250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .gpio_card_ro_invert = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static struct gpiod_lookup_table zeus_mci_gpio_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .dev_id = "pxa2xx-mci.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) GPIO_LOOKUP("gpio-pxa", ZEUS_MMC_CD_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) "cd", GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) GPIO_LOOKUP("gpio-pxa", ZEUS_MMC_WP_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) "wp", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) * USB Device Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static void zeus_udc_command(int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) case PXA2XX_UDC_CMD_DISCONNECT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) pr_info("zeus: disconnecting USB client\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) case PXA2XX_UDC_CMD_CONNECT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) pr_info("zeus: connecting USB client\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) UP2OCR = UP2OCR_HXOE | UP2OCR_DPPUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) static struct pxa2xx_udc_mach_info zeus_udc_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .udc_command = zeus_udc_command,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static struct platform_device *zeus_devices[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) &zeus_serial_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) &zeus_mtd_devices[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) &zeus_dm9k0_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) &zeus_dm9k1_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) &zeus_sram_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) &zeus_leds_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) &zeus_pcmcia_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) &zeus_max6369_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) &can_regulator_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) &zeus_ohci_regulator_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static void zeus_power_off(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) local_irq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) cpu_suspend(PWRMODE_DEEPSLEEP, pxa27x_finish_suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define zeus_power_off NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #ifdef CONFIG_APM_EMULATION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) static void zeus_get_power_status(struct apm_power_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /* Power supply is always present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) info->ac_line_status = APM_AC_ONLINE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) info->battery_status = APM_BATTERY_STATUS_NOT_PRESENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) info->battery_flag = APM_BATTERY_FLAG_NOT_PRESENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static inline void zeus_setup_apm(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) apm_get_power_status = zeus_get_power_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static inline void zeus_setup_apm(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static int zeus_get_pcb_info(struct i2c_client *client, unsigned gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) unsigned ngpio, void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) u8 pcb_info = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) int pcb_bit = gpio + i + 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (gpio_request(pcb_bit, "pcb info")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) dev_err(&client->dev, "Can't request pcb info %d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (gpio_direction_input(pcb_bit)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) dev_err(&client->dev, "Can't read pcb info %d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) gpio_free(pcb_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) pcb_info |= !!gpio_get_value(pcb_bit) << i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) gpio_free(pcb_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) dev_info(&client->dev, "Zeus PCB version %d issue %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) pcb_info >> 4, pcb_info & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static struct pca953x_platform_data zeus_pca953x_pdata[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) [0] = { .gpio_base = ZEUS_EXT0_GPIO_BASE, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .gpio_base = ZEUS_EXT1_GPIO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .setup = zeus_get_pcb_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) [2] = { .gpio_base = ZEUS_USER_GPIO_BASE, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static struct i2c_board_info __initdata zeus_i2c_devices[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) I2C_BOARD_INFO("pca9535", 0x21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .platform_data = &zeus_pca953x_pdata[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) I2C_BOARD_INFO("pca9535", 0x22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .platform_data = &zeus_pca953x_pdata[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) I2C_BOARD_INFO("pca9535", 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .platform_data = &zeus_pca953x_pdata[2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .irq = PXA_GPIO_TO_IRQ(ZEUS_EXTGPIO_GPIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) { I2C_BOARD_INFO("lm75a", 0x48) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) { I2C_BOARD_INFO("24c01", 0x50) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) { I2C_BOARD_INFO("isl1208", 0x6f) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static mfp_cfg_t zeus_pin_config[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) /* AC97 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) GPIO28_AC97_BITCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) GPIO29_AC97_SDATA_IN_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) GPIO30_AC97_SDATA_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) GPIO31_AC97_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) GPIO15_nCS_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) GPIO78_nCS_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) GPIO80_nCS_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) GPIO33_nCS_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) GPIO22_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) GPIO32_MMC_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) GPIO92_MMC_DAT_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) GPIO109_MMC_DAT_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) GPIO110_MMC_DAT_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) GPIO111_MMC_DAT_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) GPIO112_MMC_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) GPIO88_USBH1_PWR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) GPIO89_USBH1_PEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) GPIO119_USBH2_PWR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) GPIO120_USBH2_PEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) GPIO86_LCD_LDD_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) GPIO87_LCD_LDD_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) GPIO102_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) GPIO104_CIF_DD_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) GPIO105_CIF_DD_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) GPIO81_SSP3_TXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) GPIO82_SSP3_RXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) GPIO83_SSP3_SFRM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) GPIO84_SSP3_SCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) GPIO48_nPOE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) GPIO49_nPWE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) GPIO50_nPIOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) GPIO51_nPIOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) GPIO85_nPCE_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) GPIO54_nPCE_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) GPIO79_PSKTSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) GPIO55_nPREG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) GPIO56_nPWAIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) GPIO57_nIOIS16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) GPIO36_GPIO, /* CF CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) GPIO97_GPIO, /* CF PWREN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) GPIO99_GPIO, /* CF RDY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) * DM9k MSCx settings: SRAM, 16 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) * 17 cycles delay first access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) * 5 cycles delay next access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) * 13 cycles recovery time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) * faster device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) #define DM9K_MSC_VALUE 0xe4c9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) static void __init zeus_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) u16 dm9000_msc = DM9K_MSC_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) u32 msc0, msc1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) system_rev = __raw_readw(ZEUS_CPLD_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) pr_info("Zeus CPLD V%dI%d\n", (system_rev & 0xf0) >> 4, (system_rev & 0x0f));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) /* Fix timings for dm9000s (CS1/CS2)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) msc0 = (__raw_readl(MSC0) & 0x0000ffff) | (dm9000_msc << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) msc1 = (__raw_readl(MSC1) & 0xffff0000) | dm9000_msc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) __raw_writel(msc0, MSC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) __raw_writel(msc1, MSC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) pm_power_off = zeus_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) zeus_setup_apm();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) pxa2xx_mfp_config(ARRAY_AND_SIZE(zeus_pin_config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) gpiod_add_lookup_table(&can_regulator_gpiod_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) gpiod_add_lookup_table(&zeus_ohci_regulator_gpiod_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) platform_add_devices(zeus_devices, ARRAY_SIZE(zeus_devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) zeus_register_ohci();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (zeus_setup_fb_gpios())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) pr_err("Failed to setup fb gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) pxa_set_fb_info(NULL, &zeus_fb_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) gpiod_add_lookup_table(&zeus_mci_gpio_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) pxa_set_mci_info(&zeus_mci_platform_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) pxa_set_udc_info(&zeus_udc_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) pxa_set_ac97_info(&zeus_ac97_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) pxa_set_i2c_info(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) i2c_register_board_info(0, ARRAY_AND_SIZE(zeus_i2c_devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) pxa2xx_set_spi_info(3, &pxa2xx_spi_ssp3_master_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) spi_register_board_info(zeus_spi_board_info, ARRAY_SIZE(zeus_spi_board_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) regulator_has_full_constraints();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) static struct map_desc zeus_io_desc[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .virtual = (unsigned long)ZEUS_CPLD_VERSION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .pfn = __phys_to_pfn(ZEUS_CPLD_VERSION_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .length = 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .virtual = (unsigned long)ZEUS_CPLD_ISA_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .pfn = __phys_to_pfn(ZEUS_CPLD_ISA_IRQ_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .length = 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .virtual = (unsigned long)ZEUS_CPLD_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .pfn = __phys_to_pfn(ZEUS_CPLD_CONTROL_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .length = 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .virtual = (unsigned long)ZEUS_PC104IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .pfn = __phys_to_pfn(ZEUS_PC104IO_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .length = 0x00800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) static void __init zeus_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) pxa27x_map_io();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) iotable_init(zeus_io_desc, ARRAY_SIZE(zeus_io_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) /* Clear PSPR to ensure a full restart on wake-up. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) PMCR = PSPR = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) /* enable internal 32.768Khz oscillator (ignore OSCC_OOK) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) writel(readl(OSCC) | OSCC_OON, OSCC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) /* Some clock cycles later (from OSCC_ON), programme PCFR (OPDE...).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) * float chip selects and PCMCIA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) PCFR = PCFR_OPDE | PCFR_DC_EN | PCFR_FS | PCFR_FP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) MACHINE_START(ARCOM_ZEUS, "Arcom/Eurotech ZEUS")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) /* Maintainer: Marc Zyngier <maz@misterjones.org> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .atag_offset = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .map_io = zeus_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .nr_irqs = ZEUS_NR_IRQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .init_irq = zeus_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .handle_irq = pxa27x_handle_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .init_time = pxa_timer_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .init_machine = zeus_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .restart = pxa_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) MACHINE_END
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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