^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * arch/arm/mach-pxa/include/mach/viper.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Ian Campbell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Created: Feb 03, 2003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright: Arcom Control Systems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Maintained by Marc Zyngier <maz@misterjones.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * <marc.zyngier@altran.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Created based on lubbock.h:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Author: Nicolas Pitre
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Created: Jun 15, 2001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Copyright: MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #ifndef ARCH_VIPER_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ARCH_VIPER_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define VIPER_BOOT_PHYS PXA_CS0_PHYS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define VIPER_FLASH_PHYS PXA_CS1_PHYS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define VIPER_ETH_PHYS PXA_CS2_PHYS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define VIPER_USB_PHYS PXA_CS3_PHYS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define VIPER_ETH_DATA_PHYS PXA_CS4_PHYS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define VIPER_CPLD_PHYS PXA_CS5_PHYS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define VIPER_CPLD_BASE (0xf0000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define VIPER_PC104IO_BASE (0xf1000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define VIPER_USB_BASE (0xf1800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define VIPER_ETH_GPIO (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define VIPER_CPLD_GPIO (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define VIPER_USB_GPIO (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define VIPER_UARTA_GPIO (4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define VIPER_UARTB_GPIO (3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define VIPER_CF_CD_GPIO (32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define VIPER_CF_RDY_GPIO (8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define VIPER_BCKLIGHT_EN_GPIO (9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define VIPER_LCD_EN_GPIO (10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define VIPER_PSU_DATA_GPIO (6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define VIPER_PSU_CLK_GPIO (11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define VIPER_UART_SHDN_GPIO (12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define VIPER_BRIGHTNESS_GPIO (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define VIPER_PSU_nCS_LD_GPIO (19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define VIPER_UPS_GPIO (20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define VIPER_CF_POWER_GPIO (82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define VIPER_TPM_I2C_SDA_GPIO (26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define VIPER_TPM_I2C_SCL_GPIO (27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define VIPER_RTC_I2C_SDA_GPIO (83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define VIPER_RTC_I2C_SCL_GPIO (84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define VIPER_CPLD_P2V(x) ((x) - VIPER_CPLD_PHYS + VIPER_CPLD_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define VIPER_CPLD_V2P(x) ((x) - VIPER_CPLD_BASE + VIPER_CPLD_PHYS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) # define __VIPER_CPLD_REG(x) (*((volatile u16 *)VIPER_CPLD_P2V(x)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* board level registers in the CPLD: (offsets from CPLD_BASE) ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* ... Physical addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define _VIPER_LO_IRQ_STATUS (VIPER_CPLD_PHYS + 0x100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define _VIPER_ICR_PHYS (VIPER_CPLD_PHYS + 0x100002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define _VIPER_HI_IRQ_STATUS (VIPER_CPLD_PHYS + 0x100004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define _VIPER_VERSION_PHYS (VIPER_CPLD_PHYS + 0x100006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define VIPER_UARTA_PHYS (VIPER_CPLD_PHYS + 0x300010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define VIPER_UARTB_PHYS (VIPER_CPLD_PHYS + 0x300000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define _VIPER_SRAM_BASE (VIPER_CPLD_PHYS + 0x800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* ... Virtual addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define VIPER_LO_IRQ_STATUS __VIPER_CPLD_REG(_VIPER_LO_IRQ_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define VIPER_HI_IRQ_STATUS __VIPER_CPLD_REG(_VIPER_HI_IRQ_STATUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define VIPER_VERSION __VIPER_CPLD_REG(_VIPER_VERSION_PHYS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define VIPER_ICR __VIPER_CPLD_REG(_VIPER_ICR_PHYS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Decode VIPER_VERSION register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define VIPER_CPLD_REVISION(x) (((x) >> 5) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define VIPER_BOARD_VERSION(x) (((x) >> 3) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define VIPER_BOARD_ISSUE(x) (((x) >> 0) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Interrupt and Configuration Register (VIPER_ICR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* This is a write only register. Only CF_RST is used under Linux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define VIPER_ICR_RETRIG (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define VIPER_ICR_AUTO_CLR (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define VIPER_ICR_R_DIS (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define VIPER_ICR_CF_RST (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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