^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * PXA27x standby mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: David Burrage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * 2005 (c) MontaVista Software, Inc. This file is licensed under
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * the terms of the GNU General Public License version 2. This program
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * is licensed "as is" without any warranty of any kind, whether express
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/assembler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <mach/pxa2xx-regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) .text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #ifdef CONFIG_PXA27x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) ENTRY(pxa_cpu_standby)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) ldr r0, =PSSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) mov r1, #(PSSR_PH | PSSR_STS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) mov r2, #PWRMODE_STANDBY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) mov r3, #UNCACHED_PHYS_0 @ Read mem context in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) ldr ip, [r3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) b 1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .align 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 1: mcr p14, 0, r2, c7, c0, 0 @ put the system into Standby
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) str r1, [r0] @ make sure PSSR_PH/STS are clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #ifdef CONFIG_PXA3xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PXA3_MDCNFG 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PXA3_MDCNFG_DMCEN (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PXA3_DDR_HCAL 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PXA3_DDR_HCAL_HCRNG 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PXA3_DDR_HCAL_HCPROG (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PXA3_DDR_HCAL_HCEN (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PXA3_DMCIER 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PXA3_DMCIER_EDLP (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PXA3_DMCISR 0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PXA3_RCOMP 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PXA3_RCOMP_SWEVAL (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ENTRY(pm_enter_standby_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) mov r1, #0xf6000000 @ DMEMC_REG_BASE (PXA3_MDCNFG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) add r1, r1, #0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * Preload the TLB entry for accessing the dynamic memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * controller registers. Note that page table lookups will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * fail until the dynamic memory controller has been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * reinitialised - and that includes MMU page table walks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * This also means that only the dynamic memory controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * can be reliably accessed in the code following standby.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ldr r2, [r1] @ Dummy read PXA3_MDCNFG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) mcr p14, 0, r0, c7, c0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .rept 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .endr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) ldr r0, [r1, #PXA3_DDR_HCAL] @ Clear (and wait for) HCEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) bic r0, r0, #PXA3_DDR_HCAL_HCEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) str r0, [r1, #PXA3_DDR_HCAL]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 1: ldr r0, [r1, #PXA3_DDR_HCAL]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) tst r0, #PXA3_DDR_HCAL_HCEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) bne 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ldr r0, [r1, #PXA3_RCOMP] @ Initiate RCOMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) orr r0, r0, #PXA3_RCOMP_SWEVAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) str r0, [r1, #PXA3_RCOMP]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) mov r0, #~0 @ Clear interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) str r0, [r1, #PXA3_DMCISR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ldr r0, [r1, #PXA3_DMCIER] @ set DMIER[EDLP]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) orr r0, r0, #PXA3_DMCIER_EDLP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) str r0, [r1, #PXA3_DMCIER]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ldr r0, [r1, #PXA3_DDR_HCAL] @ clear HCRNG, set HCPROG, HCEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) bic r0, r0, #PXA3_DDR_HCAL_HCRNG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) orr r0, r0, #PXA3_DDR_HCAL_HCEN | PXA3_DDR_HCAL_HCPROG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) str r0, [r1, #PXA3_DDR_HCAL]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) 1: ldr r0, [r1, #PXA3_DMCISR]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) tst r0, #PXA3_DMCIER_EDLP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) beq 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ldr r0, [r1, #PXA3_MDCNFG] @ set PXA3_MDCNFG[DMCEN]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) orr r0, r0, #PXA3_MDCNFG_DMCEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) str r0, [r1, #PXA3_MDCNFG]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) 1: ldr r0, [r1, #PXA3_MDCNFG]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) tst r0, #PXA3_MDCNFG_DMCEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) beq 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ldr r0, [r1, #PXA3_DDR_HCAL] @ set PXA3_DDR_HCAL[HCRNG]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) orr r0, r0, #2 @ HCRNG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) str r0, [r1, #PXA3_DDR_HCAL]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ldr r0, [r1, #PXA3_DMCIER] @ Clear the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) bic r0, r0, #0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) str r0, [r1, #PXA3_DMCIER]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ret lr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ENTRY(pm_enter_standby_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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