Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Static Memory Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <mach/smemc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) static unsigned long msc[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static unsigned long sxcnfg, memclkcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static unsigned long csadrcfg[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static int pxa3xx_smemc_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	msc[0] = __raw_readl(MSC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	msc[1] = __raw_readl(MSC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	sxcnfg = __raw_readl(SXCNFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	memclkcfg = __raw_readl(MEMCLKCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	csadrcfg[0] = __raw_readl(CSADRCFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	csadrcfg[1] = __raw_readl(CSADRCFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	csadrcfg[2] = __raw_readl(CSADRCFG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	csadrcfg[3] = __raw_readl(CSADRCFG3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static void pxa3xx_smemc_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	__raw_writel(msc[0], MSC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	__raw_writel(msc[1], MSC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	__raw_writel(sxcnfg, SXCNFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	__raw_writel(memclkcfg, MEMCLKCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	__raw_writel(csadrcfg[0], CSADRCFG0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	__raw_writel(csadrcfg[1], CSADRCFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	__raw_writel(csadrcfg[2], CSADRCFG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	__raw_writel(csadrcfg[3], CSADRCFG3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	/* CSMSADRCFG wakes up in its default state (0), so we need to set it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	__raw_writel(0x2, CSMSADRCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static struct syscore_ops smemc_syscore_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	.suspend	= pxa3xx_smemc_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	.resume		= pxa3xx_smemc_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static int __init smemc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	if (cpu_is_pxa3xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 		 * The only documentation we have on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 		 * Chip Select Configuration Register (CSMSADRCFG) is that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 		 * it must be programmed to 0x2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 		 * Moreover, in the bit definitions, the second bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		 * (CSMSADRCFG[1]) is called "SETALWAYS".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		 * Other bits are reserved in this register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 		__raw_writel(0x2, CSMSADRCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 		register_syscore_ops(&smemc_syscore_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) subsys_initcall(smemc_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #endif