^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/mach-pxa/saar.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Support for the Marvell PXA930 Handheld Platform (aka SAAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2007-2008 Marvell International Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_data/i2c-pxa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/smc91x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mfd/da903x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/mtd/partitions.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/mtd/onenand.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/mach/flash.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "pxa930.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/platform_data/video-pxafb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "devices.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include "generic.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define GPIO_LCD_RESET (16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* SAAR MFP configurations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static mfp_cfg_t saar_mfp_cfg[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* LCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) GPIO23_LCD_DD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) GPIO24_LCD_DD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) GPIO25_LCD_DD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) GPIO26_LCD_DD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) GPIO27_LCD_DD4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) GPIO28_LCD_DD5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) GPIO29_LCD_DD6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) GPIO44_LCD_DD7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) GPIO21_LCD_CS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) GPIO22_LCD_VSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) GPIO17_LCD_FCLK_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) GPIO18_LCD_LCLK_A0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) GPIO19_LCD_PCLK_WR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) GPIO16_GPIO, /* LCD reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Ethernet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) DF_nCS1_nCS3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) GPIO97_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* DFI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) DF_INT_RnB_ND_INT_RnB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) DF_nRE_nOE_ND_nRE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) DF_nWE_ND_nWE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) DF_CLE_nOE_ND_CLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) DF_nADV1_ALE_ND_ALE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) DF_nADV2_ALE_nCS3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) DF_nCS0_ND_nCS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) DF_IO0_ND_IO0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) DF_IO1_ND_IO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) DF_IO2_ND_IO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) DF_IO3_ND_IO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) DF_IO4_ND_IO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) DF_IO5_ND_IO5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) DF_IO6_ND_IO6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) DF_IO7_ND_IO7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) DF_IO8_ND_IO8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) DF_IO9_ND_IO9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) DF_IO10_ND_IO10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) DF_IO11_ND_IO11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) DF_IO12_ND_IO12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) DF_IO13_ND_IO13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) DF_IO14_ND_IO14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) DF_IO15_ND_IO15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SAAR_ETH_PHYS (0x14000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static struct resource smc91x_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .start = (SAAR_ETH_PHYS + 0x300),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .end = (SAAR_ETH_PHYS + 0xfffff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .start = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO97)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .end = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO97)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static struct smc91x_platdata saar_smc91x_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT | SMC91X_USE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static struct platform_device smc91x_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .name = "smc91x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .num_resources = ARRAY_SIZE(smc91x_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .resource = smc91x_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .platform_data = &saar_smc91x_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static uint16_t lcd_power_on[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* single frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) SMART_CMD_NOOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) SMART_CMD(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) SMART_DELAY(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) SMART_CMD_NOOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) SMART_CMD(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) SMART_DELAY(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) SMART_CMD_NOOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) SMART_CMD(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) SMART_DELAY(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) SMART_CMD_NOOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) SMART_CMD(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) SMART_DELAY(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* calibration control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) SMART_CMD(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) SMART_CMD(0xA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) SMART_DAT(0x80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) SMART_DAT(0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) SMART_DELAY(150),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /*Power-On Init sequence*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) SMART_CMD(0x00), /* output ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) SMART_CMD(0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) SMART_DAT(0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) SMART_CMD(0x00), /* wave ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) SMART_CMD(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) SMART_DAT(0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) SMART_CMD(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) SMART_CMD(0x03), /* entry mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) SMART_DAT(0xD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) SMART_DAT(0x30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) SMART_CMD(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) SMART_CMD(0x08), /* display ctrl 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) SMART_DAT(0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) SMART_DAT(0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) SMART_CMD(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) SMART_CMD(0x09), /* display ctrl 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) SMART_DAT(0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) SMART_DAT(0x2F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) SMART_CMD(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) SMART_CMD(0x0A), /* display ctrl 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) SMART_DAT(0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) SMART_CMD(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) SMART_CMD(0x0D), /* Frame Marker position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) SMART_DAT(0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) SMART_CMD(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) SMART_CMD(0x60), /* Driver output control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) SMART_DAT(0x27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) SMART_CMD(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) SMART_CMD(0x61), /* Base image display control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) SMART_DAT(0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) SMART_CMD(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) SMART_CMD(0x30), /* Y settings 30h-3Dh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) SMART_DAT(0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) SMART_DAT(0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) SMART_CMD(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) SMART_CMD(0x31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) SMART_DAT(0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) SMART_CMD(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) SMART_CMD(0x32), /* Timing(3), ASW HOLD=0.5CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) SMART_DAT(0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) SMART_CMD(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) SMART_CMD(0x33), /* Timing(4), CKV ST=0CLK, CKV ED=1CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) SMART_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) SMART_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) SMART_CMD(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) SMART_CMD(0x34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) SMART_CMD(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) SMART_CMD(0x35),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) SMART_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) SMART_DAT(0x05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) SMART_CMD(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) SMART_CMD(0x36),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) SMART_DAT(0x1F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) SMART_DAT(0x1F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) SMART_CMD(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) SMART_CMD(0x37),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) SMART_DAT(0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) SMART_DAT(0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) SMART_CMD(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) SMART_CMD(0x38),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) SMART_DAT(0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) SMART_CMD(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) SMART_CMD(0x39),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) SMART_DAT(0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) SMART_CMD(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) SMART_CMD(0x3A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) SMART_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) SMART_DAT(0x03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) SMART_CMD(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) SMART_CMD(0x3B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) SMART_CMD(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) SMART_CMD(0x3C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) SMART_DAT(0x02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) SMART_DAT(0x05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) SMART_CMD(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) SMART_CMD(0x3D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) SMART_DAT(0x1F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) SMART_DAT(0x1F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) SMART_CMD(0x00), /* Display control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) SMART_CMD(0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) SMART_DAT(0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) SMART_CMD(0x00), /* Power control 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) SMART_CMD(0x17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) SMART_DAT(0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) SMART_CMD(0x00), /* Power control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) SMART_CMD(0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) SMART_DAT(0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) SMART_DAT(0xB0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) SMART_CMD(0x00), /* Power control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) SMART_CMD(0x11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) SMART_DAT(0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) SMART_DAT(0x30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) SMART_CMD(0x00), /* Power control 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) SMART_CMD(0x12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) SMART_DAT(0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) SMART_DAT(0x9E),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) SMART_CMD(0x00), /* Power control 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) SMART_CMD(0x13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) SMART_DAT(0x17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) SMART_CMD(0x00), /* Power control 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) SMART_CMD(0x12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) SMART_DAT(0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) SMART_DAT(0xBE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) SMART_DELAY(100),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* display mode : 240*320 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) SMART_CMD(0x00), /* RAM address set(H) 0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) SMART_CMD(0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) SMART_CMD(0x00), /* RAM address set(V) 4*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) SMART_CMD(0x21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) SMART_CMD(0x00), /* Start of Window RAM address set(H) 8*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) SMART_CMD(0x50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) SMART_CMD(0x00), /* End of Window RAM address set(H) 12*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) SMART_CMD(0x51),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) SMART_DAT(0xEF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) SMART_CMD(0x00), /* Start of Window RAM address set(V) 16*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) SMART_CMD(0x52),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) SMART_CMD(0x00), /* End of Window RAM address set(V) 20*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) SMART_CMD(0x53),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) SMART_DAT(0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) SMART_DAT(0x3F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) SMART_CMD(0x00), /* Panel interface control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) SMART_CMD(0x90),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) SMART_DAT(0x1A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) SMART_CMD(0x00), /* Panel interface control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) SMART_CMD(0x92),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) SMART_DAT(0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) SMART_CMD(0x00), /* Panel interface control 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) SMART_CMD(0x93),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) SMART_DAT(0x05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) SMART_DELAY(20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static uint16_t lcd_panel_on[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) SMART_CMD(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) SMART_CMD(0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) SMART_DAT(0x21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) SMART_DELAY(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) SMART_CMD(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) SMART_CMD(0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) SMART_DAT(0x61),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) SMART_DELAY(100),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) SMART_CMD(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) SMART_CMD(0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) SMART_DAT(0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) SMART_DAT(0x73),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) SMART_DELAY(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static uint16_t lcd_panel_off[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) SMART_CMD(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) SMART_CMD(0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) SMART_DAT(0x72),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) SMART_DELAY(40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) SMART_CMD(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) SMART_CMD(0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) SMART_DAT(0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) SMART_DELAY(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) SMART_CMD(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) SMART_CMD(0x07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) SMART_DELAY(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static uint16_t lcd_power_off[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) SMART_CMD(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) SMART_CMD(0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) SMART_DAT(0x80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) SMART_CMD(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) SMART_CMD(0x11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) SMART_DAT(0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) SMART_DAT(0x60),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) SMART_CMD(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) SMART_CMD(0x12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) SMART_DAT(0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) SMART_DAT(0xAE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) SMART_DELAY(40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) SMART_CMD(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) SMART_CMD(0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static uint16_t update_framedata[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* set display ram: 240*320 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) SMART_CMD(0x00), /* RAM address set(H) 0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) SMART_CMD(0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) SMART_CMD(0x00), /* RAM address set(V) 4*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) SMART_CMD(0x21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) SMART_CMD(0x00), /* Start of Window RAM address set(H) 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) SMART_CMD(0x50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) SMART_CMD(0x00), /* End of Window RAM address set(H) 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) SMART_CMD(0x51),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) SMART_DAT(0xEF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) SMART_CMD(0x00), /* Start of Window RAM address set(V) 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) SMART_CMD(0x52),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) SMART_DAT(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) SMART_CMD(0x00), /* End of Window RAM address set(V) 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) SMART_CMD(0x53),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) SMART_DAT(0x01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) SMART_DAT(0x3F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* wait for vsync cmd before transferring frame data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) SMART_CMD_WAIT_FOR_VSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* write ram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) SMART_CMD(0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) SMART_CMD(0x22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* write frame data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) SMART_CMD_WRITE_FRAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static void ltm022a97a_lcd_power(int on, struct fb_var_screeninfo *var)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static int pin_requested = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct fb_info *info = container_of(var, struct fb_info, var);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (!pin_requested) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) err = gpio_request(GPIO_LCD_RESET, "lcd reset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) pr_err("failed to request gpio for LCD reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) gpio_direction_output(GPIO_LCD_RESET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) pin_requested = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) gpio_set_value(GPIO_LCD_RESET, 0); msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) gpio_set_value(GPIO_LCD_RESET, 1); msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) pxafb_smart_queue(info, ARRAY_AND_SIZE(lcd_power_on));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) pxafb_smart_queue(info, ARRAY_AND_SIZE(lcd_panel_on));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) pxafb_smart_queue(info, ARRAY_AND_SIZE(lcd_panel_off));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) pxafb_smart_queue(info, ARRAY_AND_SIZE(lcd_power_off));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) err = pxafb_smart_flush(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) pr_err("%s: timed out\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static void ltm022a97a_update(struct fb_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) pxafb_smart_queue(info, ARRAY_AND_SIZE(update_framedata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) pxafb_smart_flush(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static struct pxafb_mode_info toshiba_ltm022a97a_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .xres = 240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .yres = 320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .bpp = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .a0csrd_set_hld = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .a0cswr_set_hld = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .wr_pulse_width = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .rd_pulse_width = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .op_hold_time = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .cmd_inh_time = 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* L_LCLK_A0 and L_LCLK_RD active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .sync = FB_SYNC_HOR_HIGH_ACT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) FB_SYNC_VERT_HIGH_ACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static struct pxafb_mach_info saar_lcd_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .modes = toshiba_ltm022a97a_modes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .num_modes = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .lcd_conn = LCD_SMART_PANEL_8BPP | LCD_PCLK_EDGE_FALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .pxafb_lcd_power = ltm022a97a_lcd_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .smart_update = ltm022a97a_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static void __init saar_init_lcd(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) pxa_set_fb_info(NULL, &saar_lcd_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static inline void saar_init_lcd(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static struct da9034_backlight_pdata saar_da9034_backlight = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .output_current = 4, /* 4mA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static struct da903x_subdev_info saar_da9034_subdevs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .name = "da903x-backlight",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .id = DA9034_ID_WLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .platform_data = &saar_da9034_backlight,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static struct da903x_platform_data saar_da9034_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .num_subdevs = ARRAY_SIZE(saar_da9034_subdevs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .subdevs = saar_da9034_subdevs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static struct i2c_board_info saar_i2c_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .type = "da9034",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .addr = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .platform_data = &saar_da9034_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .irq = PXA_GPIO_TO_IRQ(mfp_to_gpio(MFP_PIN_GPIO83)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static void __init saar_init_i2c(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) pxa_set_i2c_info(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) i2c_register_board_info(0, ARRAY_AND_SIZE(saar_i2c_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static inline void saar_init_i2c(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #if defined(CONFIG_MTD_ONENAND) || defined(CONFIG_MTD_ONENAND_MODULE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static struct mtd_partition saar_onenand_partitions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .name = "bootloader",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .size = SZ_1M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .mask_flags = MTD_WRITEABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .name = "reserved",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .size = SZ_128K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .mask_flags = MTD_WRITEABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .name = "reserved",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .size = SZ_8M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .mask_flags = MTD_WRITEABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .name = "kernel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .size = (SZ_2M + SZ_1M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .mask_flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .name = "filesystem",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .offset = MTDPART_OFS_APPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .size = SZ_32M + SZ_16M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .mask_flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static struct onenand_platform_data saar_onenand_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .parts = saar_onenand_partitions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .nr_parts = ARRAY_SIZE(saar_onenand_partitions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define SMC_CS0_PHYS_BASE (0x10000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static struct resource saar_resource_onenand[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .start = SMC_CS0_PHYS_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .end = SMC_CS0_PHYS_BASE + SZ_1M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static struct platform_device saar_device_onenand = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .name = "onenand-flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .platform_data = &saar_onenand_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .resource = saar_resource_onenand,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .num_resources = ARRAY_SIZE(saar_resource_onenand),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static void __init saar_init_onenand(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) platform_device_register(&saar_device_onenand);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static void __init saar_init_onenand(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static void __init saar_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /* initialize MFP configurations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) pxa3xx_mfp_config(ARRAY_AND_SIZE(saar_mfp_cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) pxa_set_ffuart_info(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) pxa_set_btuart_info(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) pxa_set_stuart_info(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) platform_device_register(&smc91x_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) saar_init_onenand();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) saar_init_i2c();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) saar_init_lcd();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) MACHINE_START(SAAR, "PXA930 Handheld Platform (aka SAAR)")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /* Maintainer: Eric Miao <eric.miao@marvell.com> */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .atag_offset = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .map_io = pxa3xx_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .nr_irqs = PXA_NR_IRQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .init_irq = pxa3xx_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .handle_irq = pxa3xx_handle_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .init_time = pxa_timer_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .init_machine = saar_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .restart = pxa_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) MACHINE_END
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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