Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #ifndef __ASM_ARCH_PXA3xx_U2D_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #define __ASM_ARCH_PXA3xx_U2D_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <mach/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * USB2 device controller registers and bits definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define U2DCR		(0x0000)	/* U2D Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define U2DCR_NDC	(1   << 31)	/* NAK During Config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define U2DCR_HSTC	(0x7 << 28)	/* High Speed Timeout Calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define U2DCR_SPEOREN	(1   << 27)	/* Short Packet EOR INTR generation Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define U2DCR_FSTC	(0x7 << 24)	/* Full Speed Timeout Calibration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define U2DCR_UCLKOVR	(1   << 22)	/* UTM Clock Override */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define U2DCR_ABP	(1   << 21)	/* Application Bus Power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define U2DCR_ADD	(1   << 20)	/* Application Device Disconnect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define U2DCR_CC	(1   << 19)	/* Configuration Change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define U2DCR_HS	(1   << 18)	/* High Speed USB Detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define U2DCR_SMAC	(1   << 17)	/* Switch Endpoint Memory to Active Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define U2DCR_DWRE	(1   << 16)	/* Device Remote Wake-up Feature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define U2DCR_ACN	(0xf << 12)	/* Active U2D Configuration Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define U2DCR_AIN	(0xf << 8)	/* Active U2D Interface Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define U2DCR_AAISN	(0xf << 4)	/* Active U2D Alternate Interface Setting Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define U2DCR_EMCE	(1   << 3)	/* Endpoint Memory Configuration Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define U2DCR_UDR	(1   << 2)	/* U2D Resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define U2DCR_UDA	(1   << 1)	/* U2D Active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define U2DCR_UDE	(1   << 0)	/* U2D Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define U2DICR			(0x0004)	/* U2D Interrupt Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define U2DISR			(0x000C)	/* U2D Interrupt Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define U2DINT_CC		(1 << 31)	/* Interrupt - Configuration Change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define U2DINT_SOF		(1 << 30)	/* Interrupt - SOF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define U2DINT_USOF		(1 << 29)	/* Interrupt - micro SOF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define U2DINT_RU		(1 << 28)	/* Interrupt - Resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define U2DINT_SU		(1 << 27)	/* Interrupt - Suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define U2DINT_RS		(1 << 26)	/* Interrupt - Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define U2DINT_DPE		(1 << 25)	/* Interrupt - Data Packet Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define U2DINT_FIFOERR		(0x4)		/* Interrupt - endpoint FIFO error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define U2DINT_PACKETCMP	(0x2)		/* Interrupt - endpoint packet complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define U2DINT_SPACKETCMP	(0x1)		/* Interrupt - endpoint short packet complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define U2DFNR			(0x0014)	/* U2D Frame Number Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define U2DINT(n, intr)		(((intr) & 0x07) << (((n) & 0x07) * 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define U2DICR2			(0x0008)	/* U2D Interrupt Control Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define U2DISR2			(0x0010)	/* U2D Interrupt Status Register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define U2DOTGCR		(0x0020)	/* U2D OTG Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define U2DOTGCR_OTGEN		(1 << 31)	/* On-The-Go Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define U2DOTGCR_AALTHNP	(1 << 30)	/* A-device Alternate Host Negotiation Protocal Port Support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define U2DOTGCR_AHNP		(1 << 29)	/* A-device Host Negotiation Protocal Support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define U2DOTGCR_BHNP		(1 << 28)	/* B-device Host Negotiation Protocal Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #ifdef CONFIG_CPU_PXA930
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define U2DOTGCR_LPA		(1 << 15)	/* ULPI low power mode active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define U2DOTGCR_IESI		(1 << 13)	/* OTG interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define U2DOTGCR_ISSI		(1 << 12)	/* OTG interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define U2DOTGCR_CKAF	(1 << 5)	/* Carkit Mode Alternate Function Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define U2DOTGCR_UTMID	(1 << 4)	/* UTMI Interface Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define U2DOTGCR_ULAF	(1 << 3)	/* ULPI Mode Alternate Function Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define U2DOTGCR_SMAF	(1 << 2)	/* Serial Mode Alternate Function Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define U2DOTGCR_RTSM	(1 << 1)	/* Return to Synchronous Mode (ULPI Mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define U2DOTGCR_ULE	(1 << 0)	/* ULPI Wrapper Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define U2DOTGICR	(0x0024)	/* U2D OTG Interrupt Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define U2DOTGISR	(0x0028)	/* U2D OTG Interrupt Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define U2DOTGINT_SF	(1 << 17)	/* OTG Set Feature Command Received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define U2DOTGINT_SI	(1 << 16)	/* OTG Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define U2DOTGINT_RLS1	(1 << 14)	/* RXCMD Linestate[1] Change Interrupt Rise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define U2DOTGINT_RLS0	(1 << 13)	/* RXCMD Linestate[0] Change Interrupt Rise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define U2DOTGINT_RID	(1 << 12)	/* RXCMD OTG ID Change Interrupt Rise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define U2DOTGINT_RSE	(1 << 11)	/* RXCMD OTG Session End Interrupt Rise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define U2DOTGINT_RSV	(1 << 10)	/* RXCMD OTG Session Valid Interrupt Rise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define U2DOTGINT_RVV	(1 << 9)	/* RXCMD OTG Vbus Valid Interrupt Rise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define U2DOTGINT_RCK	(1 << 8)	/* RXCMD Carkit Interrupt Rise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define U2DOTGINT_FLS1	(1 << 6)	/* RXCMD Linestate[1] Change Interrupt Fall */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define U2DOTGINT_FLS0	(1 << 5)	/* RXCMD Linestate[0] Change Interrupt Fall */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define U2DOTGINT_FID	(1 << 4)	/* RXCMD OTG ID Change Interrupt Fall */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define U2DOTGINT_FSE	(1 << 3)	/* RXCMD OTG Session End Interrupt Fall */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define U2DOTGINT_FSV	(1 << 2)	/* RXCMD OTG Session Valid Interrupt Fall */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define U2DOTGINT_FVV	(1 << 1)	/* RXCMD OTG Vbus Valid Interrupt Fall */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define U2DOTGINT_FCK	(1 << 0)	/* RXCMD Carkit Interrupt Fall */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define U2DOTGUSR	(0x002C)	/* U2D OTG ULPI Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define U2DOTGUSR_LPA	(1 << 31)	/* ULPI Low Power Mode Active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define U2DOTGUSR_S6A	(1 << 30)	/* ULPI Serial Mode (6-pin) Active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define U2DOTGUSR_S3A	(1 << 29)	/* ULPI Serial Mode (3-pin) Active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define U2DOTGUSR_CKA	(1 << 28)	/* ULPI Car Kit Mode Active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define U2DOTGUSR_LS1	(1 << 6)	/* RXCMD Linestate 1 Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define U2DOTGUSR_LS0	(1 << 5)	/* RXCMD Linestate 0 Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define U2DOTGUSR_ID	(1 << 4)	/* OTG IDGnd Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define U2DOTGUSR_SE	(1 << 3)	/* OTG Session End Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define U2DOTGUSR_SV	(1 << 2)	/* OTG Session Valid Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define U2DOTGUSR_VV	(1 << 1)	/* OTG Vbus Valid Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define U2DOTGUSR_CK	(1 << 0)	/* Carkit Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define U2DOTGUCR	(0x0030)	/* U2D OTG ULPI Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define U2DOTGUCR_RUN	(1    << 25)	/* RUN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define U2DOTGUCR_RNW	(1    << 24)	/* Read or Write operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define U2DOTGUCR_ADDR	(0x3f << 16)	/* Address of the ULPI PHY register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define U2DOTGUCR_WDATA	(0xff << 8)	/* The data for a WRITE command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define U2DOTGUCR_RDATA	(0xff << 0)	/* The data for a READ command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define U2DP3CR		(0x0034)	/* U2D Port 3 Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define U2DP3CR_P2SS	(0x3 << 8)	/* Host Port 2 Serial Mode Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define U2DP3CR_P3SS	(0x7 << 4)	/* Host Port 3 Serial Mode Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define U2DP3CR_VPVMBEN	(0x1 << 2)	/* Host Port 3 Vp/Vm Block Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define U2DP3CR_CFG	(0x3 << 0)	/* Host Port 3 Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define U2DCSR0		(0x0100)	/* U2D Control/Status Register - Endpoint 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define U2DCSR0_IPA	(1 << 8)	/* IN Packet Adjusted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define U2DCSR0_SA	(1 << 7)	/* SETUP Active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define U2DCSR0_RNE	(1 << 6)	/* Receive FIFO Not Empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define U2DCSR0_FST	(1 << 5)	/* Force Stall */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define U2DCSR0_SST	(1 << 4)	/* Send Stall */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define U2DCSR0_DME	(1 << 3)	/* DMA Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define U2DCSR0_FTF	(1 << 2)	/* Flush Transmit FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define U2DCSR0_IPR	(1 << 1)	/* IN Packet Ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define U2DCSR0_OPC	(1 << 0)	/* OUT Packet Complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define U2DCSR(x)	(0x0100 + ((x) << 2))	/* U2D Control/Status Register - Endpoint x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define U2DCSR_BF	(1 << 10)	/* Buffer Full, for OUT eps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define U2DCSR_BE	(1 << 10)	/* Buffer Empty, for IN eps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define U2DCSR_DPE	(1 << 9)	/* Data Packet Error, for ISO eps only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define U2DCSR_FEF	(1 << 8)	/* Flush Endpoint FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define U2DCSR_SP	(1 << 7)	/* Short Packet Control/Status, for OUT eps only, readonly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define U2DCSR_BNE	(1 << 6)	/* Buffer Not Empty, for OUT eps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define U2DCSR_BNF	(1 << 6)	/* Buffer Not Full, for IN eps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define U2DCSR_FST	(1 << 5)	/* Force STALL, write 1 set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define U2DCSR_SST	(1 << 4)	/* Sent STALL, write 1 clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define U2DCSR_DME	(1 << 3)	/* DMA Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define U2DCSR_TRN	(1 << 2)	/* Tx/Rx NAK, write 1 clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define U2DCSR_PC	(1 << 1)	/* Packet Complete, write 1 clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define U2DCSR_FS	(1 << 0)	/* FIFO needs Service */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define U2DBCR0		(0x0200)		/* U2D Byte Count Register - Endpoint 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define U2DBCR(x)	(0x0200 + ((x) << 2))	/* U2D Byte Count Register - Endpoint x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define U2DDR0		(0x0300)		/* U2D Data Register - Endpoint 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define U2DEPCR(x)	(0x0400 + ((x) << 2))	/* U2D Configuration Register - Endpoint x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define U2DEPCR_EE	(1 << 0)		/* Endpoint Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define U2DEPCR_BS_MASK	(0x3FE)			/* Buffer Size, BS*8=FIFO size, max 8184B = 8KB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define U2DSCA		(0x0500)		/* U2D Setup Command Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define U2DSCA_VALUE	(0x0120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define U2DEN0		(0x0504)		/* U2D Endpoint Information Register - Endpoint 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define U2DEN(x)	(0x0504 + ((x) << 2))	/* U2D Endpoint Information Register - Endpoint x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* U2DMA registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define U2DMACSR0		(0x1000)	/* U2DMA Control/Status Register - Channel 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define U2DMACSR(x)		(0x1000 + ((x) << 2))	/* U2DMA Control/Status Register - Channel x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define U2DMACSR_RUN		(1 << 31)	/* Run Bit (read / write) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define U2DMACSR_STOPIRQEN	(1 << 29)	/* Stop Interrupt Enable (read / write) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define U2DMACSR_EORIRQEN	(1 << 28)	/* End of Receive Interrupt Enable (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define U2DMACSR_EORJMPEN	(1 << 27)	/* Jump to next descriptor on EOR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define U2DMACSR_EORSTOPEN	(1 << 26)	/* STOP on an EOR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define U2DMACSR_RASIRQEN	(1 << 23)	/* Request After Cnannel Stopped Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define U2DMACSR_MASKRUN	(1 << 22)	/* Mask Run */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define U2DMACSR_SCEMC		(3 << 18)	/* System Bus Split Completion Error Message Class */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define U2DMACSR_SCEMI		(0x1f << 13)	/* System Bus Split Completion Error Message Index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define U2DMACSR_BUSERRTYPE	(7 << 10)	/* PX Bus Error Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define U2DMACSR_EORINTR	(1 << 9)	/* End Of Receive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define U2DMACSR_REQPEND	(1 << 8)	/* Request Pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define U2DMACSR_RASINTR	(1 << 4)	/* Request After Channel Stopped (read / write 1 clear) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define U2DMACSR_STOPINTR	(1 << 3)	/* Stop Interrupt (read only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define U2DMACSR_ENDINTR	(1 << 2)	/* End Interrupt (read / write 1 clear) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define U2DMACSR_STARTINTR	(1 << 1)	/* Start Interrupt (read / write 1 clear) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define U2DMACSR_BUSERRINTR	(1 << 0)	/* Bus Error Interrupt (read / write 1 clear) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define U2DMACR		(0x1080)		/* U2DMA Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define U2DMAINT	(0x10F0)		/* U2DMA Interrupt Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define U2DMABR0	(0x1100)		/* U2DMA Branch Register - Channel 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define U2DMABR(x)      (0x1100 + (x) << 2)	/* U2DMA Branch Register - Channel x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define U2DMADADR0      (0x1200)		/* U2DMA Descriptor Address Register - Channel 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define U2DMADADR(x)    (0x1200 + (x) * 0x10)	/* U2DMA Descriptor Address Register - Channel x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define U2DMADADR_STOP	(1U << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define U2DMASADR0	(0x1204)		/* U2DMA Source Address Register - Channel 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define U2DMASADR(x)	(0x1204 + (x) * 0x10)	/* U2DMA Source Address Register - Channel x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define U2DMATADR0	(0x1208)		/* U2DMA Target Address Register - Channel 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define U2DMATADR(x)	(0x1208 + (x) * 0x10)	/* U2DMA Target Address Register - Channel x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define U2DMACMDR0	(0x120C)		/* U2DMA Command Address Register - Channel 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define U2DMACMDR(x)	(0x120C + (x) * 0x10)	/* U2DMA Command Address Register - Channel x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define U2DMACMDR_XFRDIS	(1 << 31)	/* Transfer Direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define U2DMACMDR_STARTIRQEN	(1 << 22)	/* Start Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define U2DMACMDR_ENDIRQEN	(1 << 21)	/* End Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define U2DMACMDR_PACKCOMP	(1 << 13)	/* Packet Complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define U2DMACMDR_LEN		(0x07ff)	/* length mask (max = 2K - 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #endif /* __ASM_ARCH_PXA3xx_U2D_H */