^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __ASM_MACH_REGS_RTC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __ASM_MACH_REGS_RTC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Real Time Clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define RCNR __REG(0x40900000) /* RTC Count Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define RTAR __REG(0x40900004) /* RTC Alarm Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define RTSR __REG(0x40900008) /* RTC Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RTSR_HZE (1 << 3) /* HZ interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define RTSR_AL (1 << 0) /* RTC alarm detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #endif /* __ASM_MACH_REGS_RTC_H */