Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * linux/arch/arm/mach-pxa/pxa3xx.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * code specific to pxa3xx aka Monahans
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2006 Marvell International Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * 2007-09-02: eric miao <eric.miao@marvell.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *             initial version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/dma/pxa-dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/gpio-pxa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/platform_data/i2c-pxa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/platform_data/mmp_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <asm/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <mach/pxa3xx-regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include <mach/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include <linux/platform_data/usb-ohci-pxa27x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #include "pm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #include <mach/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #include <mach/smemc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #include <mach/irqs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #include "generic.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #include "devices.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define PECR_IE(n)	((1 << ((n) * 2)) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define PECR_IS(n)	((1 << ((n) * 2)) << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  * NAND NFC: DFI bus arbitration subset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define NDCR			(*(volatile u32 __iomem*)(NAND_VIRT + 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define NDCR_ND_ARB_EN		(1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define NDCR_ND_ARB_CNTL	(1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define ISRAM_START	0x5c000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define ISRAM_SIZE	SZ_256K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static void __iomem *sram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) static unsigned long wakeup_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  * Enter a standby mode (S0D1C2 or S0D2C2).  Upon wakeup, the dynamic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  * memory controller has to be reinitialised, so we place some code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  * in the SRAM to perform this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  * We disable FIQs across the standby - otherwise, we might receive a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  * FIQ while the SDRAM is unavailable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) static void pxa3xx_cpu_standby(unsigned int pwrmode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	memcpy_toio(sram + 0x8000, pm_enter_standby_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		    pm_enter_standby_end - pm_enter_standby_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	AD2D0SR = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	AD2D1SR = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	AD2D0ER = wakeup_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	AD2D1ER = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	ASCR = ASCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	ARSR = ARSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	local_fiq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	fn(pwrmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	local_fiq_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	AD2D0ER = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	AD2D1ER = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93)  * NOTE:  currently, the OBM (OEM Boot Module) binary comes along with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94)  * PXA3xx development kits assumes that the resuming process continues
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95)  * with the address stored within the first 4 bytes of SDRAM. The PSPR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96)  * register is used privately by BootROM and OBM, and _must_ be set to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)  * 0x5c014000 for the moment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) static void pxa3xx_cpu_pm_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	volatile unsigned long *p = (volatile void *)0xc0000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	unsigned long saved_data = *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #ifndef CONFIG_IWMMXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	u64 acc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	asm volatile(".arch_extension xscale\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		     "mra %Q0, %R0, acc0" : "=r" (acc0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	/* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	CKENB |= 1 << (CKEN_HSIO2 & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	/* clear and setup wakeup source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	AD3SR = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	AD3ER = wakeup_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	ASCR = ASCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	ARSR = ARSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	PCFR |= (1u << 13);			/* L1_DIS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	PCFR &= ~((1u << 12) | (1u << 1));	/* L0_EN | SL_ROD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	PSPR = 0x5c014000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	/* overwrite with the resume address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	*p = __pa_symbol(cpu_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	cpu_suspend(0, pxa3xx_finish_suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	*p = saved_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	AD3ER = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #ifndef CONFIG_IWMMXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	asm volatile(".arch_extension xscale\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		     "mar acc0, %Q0, %R0" : "=r" (acc0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static void pxa3xx_cpu_pm_enter(suspend_state_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	 * Don't sleep if no wakeup sources are defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	if (wakeup_src == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		printk(KERN_ERR "Not suspending: no wakeup sources\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	switch (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	case PM_SUSPEND_STANDBY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	case PM_SUSPEND_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		pxa3xx_cpu_pm_suspend();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int pxa3xx_cpu_pm_valid(suspend_state_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	.valid		= pxa3xx_cpu_pm_valid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	.enter		= pxa3xx_cpu_pm_enter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static void __init pxa3xx_init_pm(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	sram = ioremap(ISRAM_START, ISRAM_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	if (!sram) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	 * Since we copy wakeup code into the SRAM, we need to ensure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	 * that it is preserved over the low power modes.  Note: bit 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	 * is undocumented in the developer manual, but must be set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	AD1R |= ADXR_L2 | ADXR_R0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	AD2R |= ADXR_L2 | ADXR_R0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	AD3R |= ADXR_L2 | ADXR_R0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	 * Clear the resume enable registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	AD1D0ER = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	AD2D0ER = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	AD2D1ER = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	AD3ER = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int pxa3xx_set_wake(struct irq_data *d, unsigned int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	unsigned long flags, mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	switch (d->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	case IRQ_SSP3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		mask = ADXER_MFP_WSSP3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	case IRQ_MSL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		mask = ADXER_WMSL0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	case IRQ_USBH2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	case IRQ_USBH1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		mask = ADXER_WUSBH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	case IRQ_KEYPAD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		mask = ADXER_WKP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	case IRQ_AC97:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		mask = ADXER_MFP_WAC97;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	case IRQ_USIM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		mask = ADXER_WUSIM0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	case IRQ_SSP2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		mask = ADXER_MFP_WSSP2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	case IRQ_I2C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		mask = ADXER_MFP_WI2C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	case IRQ_STUART:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		mask = ADXER_MFP_WUART3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	case IRQ_BTUART:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		mask = ADXER_MFP_WUART2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	case IRQ_FFUART:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		mask = ADXER_MFP_WUART1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	case IRQ_MMC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		mask = ADXER_MFP_WMMC1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	case IRQ_SSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		mask = ADXER_MFP_WSSP1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	case IRQ_RTCAlrm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		mask = ADXER_WRTC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	case IRQ_SSP4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		mask = ADXER_MFP_WSSP4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	case IRQ_TSI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		mask = ADXER_WTSI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	case IRQ_USIM2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		mask = ADXER_WUSIM1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	case IRQ_MMC2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		mask = ADXER_MFP_WMMC2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	case IRQ_NAND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		mask = ADXER_MFP_WFLASH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	case IRQ_USB2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		mask = ADXER_WUSB2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	case IRQ_WAKEUP0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		mask = ADXER_WEXTWAKE0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	case IRQ_WAKEUP1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		mask = ADXER_WEXTWAKE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	case IRQ_MMC3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		mask = ADXER_MFP_GEN12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		wakeup_src |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		wakeup_src &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static inline void pxa3xx_init_pm(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define pxa3xx_set_wake	NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static void pxa_ack_ext_wakeup(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	PECR |= PECR_IS(d->irq - IRQ_WAKEUP0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static void pxa_mask_ext_wakeup(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	pxa_mask_irq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static void pxa_unmask_ext_wakeup(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	pxa_unmask_irq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	PECR |= PECR_IE(d->irq - IRQ_WAKEUP0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static int pxa_set_ext_wakeup_type(struct irq_data *d, unsigned int flow_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	if (flow_type & IRQ_TYPE_EDGE_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		PWER |= 1 << (d->irq - IRQ_WAKEUP0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	if (flow_type & IRQ_TYPE_EDGE_FALLING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		PWER |= 1 << (d->irq - IRQ_WAKEUP0 + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static struct irq_chip pxa_ext_wakeup_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	.name		= "WAKEUP",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	.irq_ack	= pxa_ack_ext_wakeup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	.irq_mask	= pxa_mask_ext_wakeup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	.irq_unmask	= pxa_unmask_ext_wakeup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	.irq_set_type	= pxa_set_ext_wakeup_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static void __init pxa_init_ext_wakeup_irq(int (*fn)(struct irq_data *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 					   unsigned int))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 					 handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		irq_clear_status_flags(irq, IRQ_NOREQUEST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	pxa_ext_wakeup_chip.irq_set_wake = fn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static void __init __pxa3xx_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	/* enable CP6 access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	__asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	value |= (1 << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	__asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) void __init pxa3xx_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	__pxa3xx_init_irq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	pxa_init_irq(56, pxa3xx_set_wake);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static int __init __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) pxa3xx_dt_init_irq(struct device_node *node, struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	__pxa3xx_init_irq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	pxa_dt_irq_init(pxa3xx_set_wake);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	set_handle_irq(ichp_handle_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) IRQCHIP_DECLARE(pxa3xx_intc, "marvell,pxa-intc", pxa3xx_dt_init_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #endif	/* CONFIG_OF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static struct map_desc pxa3xx_io_desc[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	{	/* Mem Ctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		.virtual	= (unsigned long)SMEMC_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		.pfn		= __phys_to_pfn(PXA3XX_SMEMC_BASE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		.length		= SMEMC_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		.type		= MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	}, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		.virtual	= (unsigned long)NAND_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		.pfn		= __phys_to_pfn(NAND_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		.length		= NAND_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		.type		= MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) void __init pxa3xx_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	pxa_map_io();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	pxa3xx_get_clk_frequency_khz(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)  * device registration specific to PXA3xx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	pxa_register_device(&pxa3xx_device_i2c_power, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static struct pxa_gpio_platform_data pxa3xx_gpio_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	.irq_base	= PXA_GPIO_TO_IRQ(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static struct platform_device *devices[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	&pxa27x_device_udc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	&pxa_device_pmu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	&pxa_device_i2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	&pxa_device_asoc_ssp1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	&pxa_device_asoc_ssp2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	&pxa_device_asoc_ssp3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	&pxa_device_asoc_ssp4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	&pxa_device_asoc_platform,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	&pxa_device_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	&pxa3xx_device_ssp1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	&pxa3xx_device_ssp2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	&pxa3xx_device_ssp3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	&pxa3xx_device_ssp4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	&pxa27x_device_pwm0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	&pxa27x_device_pwm1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static const struct dma_slave_map pxa3xx_slave_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	/* PXA25x, PXA27x and PXA3xx common entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	{ "pxa2xx-ac97", "pcm_pcm_mic_mono", PDMA_FILTER_PARAM(LOWEST, 8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	{ "pxa2xx-ac97", "pcm_pcm_aux_mono_in", PDMA_FILTER_PARAM(LOWEST, 9) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	{ "pxa2xx-ac97", "pcm_pcm_aux_mono_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	  PDMA_FILTER_PARAM(LOWEST, 10) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	{ "pxa2xx-ac97", "pcm_pcm_stereo_in", PDMA_FILTER_PARAM(LOWEST, 11) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	{ "pxa2xx-ac97", "pcm_pcm_stereo_out", PDMA_FILTER_PARAM(LOWEST, 12) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	{ "pxa-ssp-dai.0", "rx", PDMA_FILTER_PARAM(LOWEST, 13) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	{ "pxa-ssp-dai.0", "tx", PDMA_FILTER_PARAM(LOWEST, 14) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	{ "pxa-ssp-dai.1", "rx", PDMA_FILTER_PARAM(LOWEST, 15) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	{ "pxa-ssp-dai.1", "tx", PDMA_FILTER_PARAM(LOWEST, 16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	{ "pxa2xx-ir", "rx", PDMA_FILTER_PARAM(LOWEST, 17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	{ "pxa2xx-ir", "tx", PDMA_FILTER_PARAM(LOWEST, 18) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	{ "pxa2xx-mci.0", "rx", PDMA_FILTER_PARAM(LOWEST, 21) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	{ "pxa2xx-mci.0", "tx", PDMA_FILTER_PARAM(LOWEST, 22) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	{ "pxa-ssp-dai.2", "rx", PDMA_FILTER_PARAM(LOWEST, 66) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	{ "pxa-ssp-dai.2", "tx", PDMA_FILTER_PARAM(LOWEST, 67) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	/* PXA3xx specific map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	{ "pxa-ssp-dai.3", "rx", PDMA_FILTER_PARAM(LOWEST, 2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	{ "pxa-ssp-dai.3", "tx", PDMA_FILTER_PARAM(LOWEST, 3) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	{ "pxa2xx-mci.1", "rx", PDMA_FILTER_PARAM(LOWEST, 93) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	{ "pxa2xx-mci.1", "tx", PDMA_FILTER_PARAM(LOWEST, 94) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	{ "pxa3xx-nand", "data", PDMA_FILTER_PARAM(LOWEST, 97) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	{ "pxa2xx-mci.2", "rx", PDMA_FILTER_PARAM(LOWEST, 100) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	{ "pxa2xx-mci.2", "tx", PDMA_FILTER_PARAM(LOWEST, 101) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static struct mmp_dma_platdata pxa3xx_dma_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	.dma_channels	= 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	.nb_requestors	= 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	.slave_map	= pxa3xx_slave_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	.slave_map_cnt	= ARRAY_SIZE(pxa3xx_slave_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static int __init pxa3xx_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	if (cpu_is_pxa3xx()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 		reset_status = ARSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 		 * clear RDH bit every time after reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 		 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 		 * Note: the last 3 bits DxS are write-1-to-clear so carefully
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 		 * preserve them here in case they will be referenced later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 		ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 		 * Disable DFI bus arbitration, to prevent a system bus lock if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 		 * somebody disables the NAND clock (unused clock) while this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 		 * bit remains set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 		NDCR = (NDCR & ~NDCR_ND_ARB_EN) | NDCR_ND_ARB_CNTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 		pxa3xx_init_pm();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 		enable_irq_wake(IRQ_WAKEUP0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 		if (cpu_is_pxa320())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 			enable_irq_wake(IRQ_WAKEUP1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 		register_syscore_ops(&pxa_irq_syscore_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 		register_syscore_ops(&pxa3xx_mfp_syscore_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 		if (of_have_populated_dt())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 		pxa2xx_set_dmac_info(&pxa3xx_dma_pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 		ret = platform_add_devices(devices, ARRAY_SIZE(devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 		if (cpu_is_pxa300() || cpu_is_pxa310() || cpu_is_pxa320()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 			platform_device_add_data(&pxa3xx_device_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 						 &pxa3xx_gpio_pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 						 sizeof(pxa3xx_gpio_pdata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 			ret = platform_device_register(&pxa3xx_device_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) postcore_initcall(pxa3xx_init);