Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * linux/arch/arm/mach-pxa/pxa3xx-ulpi.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * code specific to pxa3xx aka Monahans
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2010 CompuLab Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * 2010-13-07: Igor Grinberg <grinberg@compulab.co.il>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *             initial version: pxa310 USB Host mode support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/usb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/usb/otg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include "regs-u2d.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <linux/platform_data/usb-pxa3xx-ulpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) struct pxa3xx_u2d_ulpi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	struct clk		*clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	void __iomem		*mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	struct usb_phy		*otg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	unsigned int		ulpi_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static struct pxa3xx_u2d_ulpi *u2d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) static inline u32 u2d_readl(u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	return __raw_readl(u2d->mmio_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) static inline void u2d_writel(u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	__raw_writel(val, u2d->mmio_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #if defined(CONFIG_PXA310_ULPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) enum u2d_ulpi_phy_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	SYNCH		= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	CARKIT		= (1 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	SER_3PIN	= (1 << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	SER_6PIN	= (1 << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	LOWPOWER	= (1 << 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) static inline enum u2d_ulpi_phy_mode pxa310_ulpi_get_phymode(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	return (u2d_readl(U2DOTGUSR) >> 28) & 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) static int pxa310_ulpi_poll(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	int timeout = 50000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	while (timeout--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		if (!(u2d_readl(U2DOTGUCR) & U2DOTGUCR_RUN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	pr_warn("%s: ULPI access timed out!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) static int pxa310_ulpi_read(struct usb_phy *otg, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	if (pxa310_ulpi_get_phymode() != SYNCH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		pr_warn("%s: PHY is not in SYNCH mode!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	u2d_writel(U2DOTGUCR, U2DOTGUCR_RUN | U2DOTGUCR_RNW | (reg << 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	err = pxa310_ulpi_poll();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	return u2d_readl(U2DOTGUCR) & U2DOTGUCR_RDATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) static int pxa310_ulpi_write(struct usb_phy *otg, u32 val, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	if (pxa310_ulpi_get_phymode() != SYNCH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		pr_warn("%s: PHY is not in SYNCH mode!\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	u2d_writel(U2DOTGUCR, U2DOTGUCR_RUN | (reg << 16) | (val << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	return pxa310_ulpi_poll();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct usb_phy_io_ops pxa310_ulpi_access_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	.read	= pxa310_ulpi_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	.write	= pxa310_ulpi_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static void pxa310_otg_transceiver_rtsm(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	u32 u2dotgcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	/* put PHY to sync mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	u2dotgcr = u2d_readl(U2DOTGCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	u2dotgcr |=  U2DOTGCR_RTSM | U2DOTGCR_UTMID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	u2d_writel(U2DOTGCR, u2dotgcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	/* setup OTG sync mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	u2dotgcr = u2d_readl(U2DOTGCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	u2dotgcr |= U2DOTGCR_ULAF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	u2dotgcr &= ~(U2DOTGCR_SMAF | U2DOTGCR_CKAF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	u2d_writel(U2DOTGCR, u2dotgcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int pxa310_start_otg_host_transcvr(struct usb_bus *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	pxa310_otg_transceiver_rtsm();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	err = usb_phy_init(u2d->otg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		pr_err("OTG transceiver init failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	err = otg_set_vbus(u2d->otg->otg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		pr_err("OTG transceiver VBUS set failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	err = otg_set_host(u2d->otg->otg, host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		pr_err("OTG transceiver Host mode set failed");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int pxa310_start_otg_hc(struct usb_bus *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	u32 u2dotgcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	/* disable USB device controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	u2d_writel(U2DCR, u2d_readl(U2DCR) & ~U2DCR_UDE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	u2d_writel(U2DOTGCR, u2d_readl(U2DOTGCR) | U2DOTGCR_UTMID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	u2d_writel(U2DOTGICR, u2d_readl(U2DOTGICR) & ~0x37F7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	err = pxa310_start_otg_host_transcvr(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	/* set xceiver mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	if (u2d->ulpi_mode & ULPI_IC_6PIN_SERIAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		u2d_writel(U2DP3CR, u2d_readl(U2DP3CR) & ~U2DP3CR_P2SS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	else if (u2d->ulpi_mode & ULPI_IC_3PIN_SERIAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		u2d_writel(U2DP3CR, u2d_readl(U2DP3CR) | U2DP3CR_P2SS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	/* start OTG host controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	u2dotgcr = u2d_readl(U2DOTGCR) | U2DOTGCR_SMAF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	u2d_writel(U2DOTGCR, u2dotgcr & ~(U2DOTGCR_ULAF | U2DOTGCR_CKAF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static void pxa310_stop_otg_hc(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	pxa310_otg_transceiver_rtsm();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	otg_set_host(u2d->otg->otg, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	otg_set_vbus(u2d->otg->otg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	usb_phy_shutdown(u2d->otg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static void pxa310_u2d_setup_otg_hc(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	u32 u2dotgcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	u2dotgcr = u2d_readl(U2DOTGCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	u2dotgcr |= U2DOTGCR_ULAF | U2DOTGCR_UTMID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	u2dotgcr &= ~(U2DOTGCR_SMAF | U2DOTGCR_CKAF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	u2d_writel(U2DOTGCR, u2dotgcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	u2d_writel(U2DOTGCR, u2dotgcr | U2DOTGCR_ULE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	msleep(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	u2d_writel(U2DOTGICR, u2d_readl(U2DOTGICR) & ~0x37F7F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int pxa310_otg_init(struct pxa3xx_u2d_platform_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	unsigned int ulpi_mode = ULPI_OTG_DRVVBUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	if (pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		if (pdata->ulpi_mode & ULPI_SER_6PIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 			ulpi_mode |= ULPI_IC_6PIN_SERIAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		else if (pdata->ulpi_mode & ULPI_SER_3PIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			ulpi_mode |= ULPI_IC_3PIN_SERIAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	u2d->ulpi_mode = ulpi_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	u2d->otg = otg_ulpi_create(&pxa310_ulpi_access_ops, ulpi_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	if (!u2d->otg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	u2d->otg->io_priv = u2d->mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static void pxa310_otg_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	kfree(u2d->otg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static inline void pxa310_u2d_setup_otg_hc(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static inline int pxa310_start_otg_hc(struct usb_bus *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static inline void pxa310_stop_otg_hc(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static inline int pxa310_otg_init(struct pxa3xx_u2d_platform_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static inline void pxa310_otg_exit(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #endif /* CONFIG_PXA310_ULPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) int pxa3xx_u2d_start_hc(struct usb_bus *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	/* In case the PXA3xx ULPI isn't used, do nothing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	if (!u2d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	clk_prepare_enable(u2d->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	if (cpu_is_pxa310()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		pxa310_u2d_setup_otg_hc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		err = pxa310_start_otg_hc(host);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) EXPORT_SYMBOL_GPL(pxa3xx_u2d_start_hc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) void pxa3xx_u2d_stop_hc(struct usb_bus *host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	/* In case the PXA3xx ULPI isn't used, do nothing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	if (!u2d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	if (cpu_is_pxa310())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		pxa310_stop_otg_hc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	clk_disable_unprepare(u2d->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) EXPORT_SYMBOL_GPL(pxa3xx_u2d_stop_hc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static int pxa3xx_u2d_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	struct pxa3xx_u2d_platform_data *pdata = pdev->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	u2d = kzalloc(sizeof(*u2d), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	if (!u2d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	u2d->clk = clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	if (IS_ERR(u2d->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		dev_err(&pdev->dev, "failed to get u2d clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		err = PTR_ERR(u2d->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		goto err_free_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	if (!r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		dev_err(&pdev->dev, "no IO memory resource defined\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		goto err_put_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)         r = request_mem_region(r->start, resource_size(r), pdev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)         if (!r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)                 dev_err(&pdev->dev, "failed to request memory resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)                 err = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)                 goto err_put_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)         }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	u2d->mmio_base = ioremap(r->start, resource_size(r));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	if (!u2d->mmio_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		dev_err(&pdev->dev, "ioremap() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		goto err_free_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	if (pdata->init) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		err = pdata->init(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 			goto err_free_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	/* Only PXA310 U2D has OTG functionality */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	if (cpu_is_pxa310()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		err = pxa310_otg_init(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 			goto err_free_plat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	platform_set_drvdata(pdev, u2d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) err_free_plat:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	if (pdata->exit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		pdata->exit(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) err_free_io:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	iounmap(u2d->mmio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) err_free_res:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	release_mem_region(r->start, resource_size(r));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) err_put_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	clk_put(u2d->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) err_free_mem:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	kfree(u2d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static int pxa3xx_u2d_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	struct pxa3xx_u2d_platform_data *pdata = pdev->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	if (cpu_is_pxa310()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		pxa310_stop_otg_hc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		pxa310_otg_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	if (pdata->exit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		pdata->exit(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	platform_set_drvdata(pdev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	iounmap(u2d->mmio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	release_mem_region(r->start, resource_size(r));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	clk_put(u2d->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	kfree(u2d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static struct platform_driver pxa3xx_u2d_ulpi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)         .driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)                 .name   = "pxa3xx-u2d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)         },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)         .probe          = pxa3xx_u2d_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)         .remove         = pxa3xx_u2d_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) module_platform_driver(pxa3xx_u2d_ulpi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) MODULE_DESCRIPTION("PXA3xx U2D ULPI driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) MODULE_AUTHOR("Igor Grinberg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) MODULE_LICENSE("GPL v2");