^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/mach-pxa/pxa27x.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Nicolas Pitre
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Created: Nov 05, 2002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright: MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Code specific to PXA27x aka Bulverde.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/dma/pxa-dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/gpio-pxa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/platform_data/i2c-pxa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/platform_data/mmp_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <mach/irqs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "pxa27x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <mach/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/platform_data/usb-ohci-pxa27x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include "pm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <mach/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <mach/smemc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include "generic.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include "devices.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) void pxa27x_clear_otgph(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) PSSR |= PSSR_OTGPH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) EXPORT_SYMBOL(pxa27x_clear_otgph);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static unsigned long ac97_reset_config[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) GPIO113_AC97_nRESET_GPIO_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) GPIO113_AC97_nRESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) GPIO95_AC97_nRESET_GPIO_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) GPIO95_AC97_nRESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * This helper function is used to work around a bug in the pxa27x's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * ac97 controller during a warm reset. The configuration of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * reset_gpio is changed as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * to_gpio == true: configured to generic output gpio and driven high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * to_gpio == false: configured to ac97 controller alt fn AC97_nRESET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (reset_gpio == 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) pxa2xx_mfp_config(to_gpio ? &ac97_reset_config[0] :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) &ac97_reset_config[1], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (reset_gpio == 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) pxa2xx_mfp_config(to_gpio ? &ac97_reset_config[2] :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) &ac97_reset_config[3], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) EXPORT_SYMBOL_GPL(pxa27x_configure_ac97reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * allow platforms to override default PWRMODE setting used for PM_SUSPEND_MEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static unsigned int pwrmode = PWRMODE_SLEEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int pxa27x_set_pwrmode(unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) case PWRMODE_SLEEP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) case PWRMODE_DEEPSLEEP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) pwrmode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * List of global PXA peripheral registers to preserve.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * More ones like CP and general purpose register values are preserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * with the stack pointer in sleep.S.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) SLEEP_SAVE_PSTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) SLEEP_SAVE_MDREFR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) SLEEP_SAVE_PCFR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) SLEEP_SAVE_COUNT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) void pxa27x_cpu_pm_save(unsigned long *sleep_save)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) sleep_save[SLEEP_SAVE_MDREFR] = __raw_readl(MDREFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) SAVE(PCFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) SAVE(PSTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) __raw_writel(sleep_save[SLEEP_SAVE_MDREFR], MDREFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) RESTORE(PCFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) PSSR = PSSR_RDH | PSSR_PH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) RESTORE(PSTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) void pxa27x_cpu_pm_enter(suspend_state_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) extern void pxa_cpu_standby(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #ifndef CONFIG_IWMMXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u64 acc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) asm volatile(".arch_extension xscale\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) "mra %Q0, %R0, acc0" : "=r" (acc0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* ensure voltage-change sequencer not initiated, which hangs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) PCFR &= ~PCFR_FVC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Clear edge-detect status register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) PEDR = 0xDF12FE1B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Clear reset status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) switch (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) case PM_SUSPEND_STANDBY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) pxa_cpu_standby();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) case PM_SUSPEND_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) cpu_suspend(pwrmode, pxa27x_finish_suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #ifndef CONFIG_IWMMXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) asm volatile(".arch_extension xscale\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) "mar acc0, %Q0, %R0" : "=r" (acc0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int pxa27x_cpu_pm_valid(suspend_state_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int pxa27x_cpu_pm_prepare(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* set resume return address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) PSPR = __pa_symbol(cpu_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static void pxa27x_cpu_pm_finish(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* ensure not to come back here if it wasn't intended */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) PSPR = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .save_count = SLEEP_SAVE_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .save = pxa27x_cpu_pm_save,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .restore = pxa27x_cpu_pm_restore,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .valid = pxa27x_cpu_pm_valid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .enter = pxa27x_cpu_pm_enter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .prepare = pxa27x_cpu_pm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .finish = pxa27x_cpu_pm_finish,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static void __init pxa27x_init_pm(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static inline void pxa27x_init_pm(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* PXA27x: Various gpios can issue wakeup events. This logic only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * handles the simple cases, not the WEMUX2 and WEMUX3 options
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static int pxa27x_set_wake(struct irq_data *d, unsigned int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) int gpio = pxa_irq_to_gpio(d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) uint32_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (gpio >= 0 && gpio < 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return gpio_set_wake(gpio, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (d->irq == IRQ_KEYPAD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return keypad_set_wake(on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) switch (d->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) case IRQ_RTCAlrm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) mask = PWER_RTC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) case IRQ_USB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) mask = 1u << 26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) PWER |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) PWER &=~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) void __init pxa27x_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) pxa_init_irq(34, pxa27x_set_wake);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static int __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) pxa27x_dt_init_irq(struct device_node *node, struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) pxa_dt_irq_init(pxa27x_set_wake);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) set_handle_irq(ichp_handle_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) IRQCHIP_DECLARE(pxa27x_intc, "marvell,pxa-intc", pxa27x_dt_init_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static struct map_desc pxa27x_io_desc[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) { /* Mem Ctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .virtual = (unsigned long)SMEMC_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .pfn = __phys_to_pfn(PXA2XX_SMEMC_BASE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .length = SMEMC_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }, { /* UNCACHED_PHYS_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .virtual = UNCACHED_PHYS_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .pfn = __phys_to_pfn(0x00000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .length = UNCACHED_PHYS_0_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) void __init pxa27x_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) pxa_map_io();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) iotable_init(ARRAY_AND_SIZE(pxa27x_io_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) pxa27x_get_clk_frequency_khz(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * device registration specific to PXA27x.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) local_irq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) PCFR |= PCFR_PI2CEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) local_irq_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) pxa_register_device(&pxa27x_device_i2c_power, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static struct pxa_gpio_platform_data pxa27x_gpio_info __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .irq_base = PXA_GPIO_TO_IRQ(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .gpio_set_wake = gpio_set_wake,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static struct platform_device *devices[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) &pxa27x_device_udc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) &pxa_device_pmu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) &pxa_device_i2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) &pxa_device_asoc_ssp1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) &pxa_device_asoc_ssp2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) &pxa_device_asoc_ssp3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) &pxa_device_asoc_platform,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) &pxa_device_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) &pxa27x_device_ssp1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) &pxa27x_device_ssp2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) &pxa27x_device_ssp3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) &pxa27x_device_pwm0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) &pxa27x_device_pwm1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static const struct dma_slave_map pxa27x_slave_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* PXA25x, PXA27x and PXA3xx common entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) { "pxa2xx-ac97", "pcm_pcm_mic_mono", PDMA_FILTER_PARAM(LOWEST, 8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) { "pxa2xx-ac97", "pcm_pcm_aux_mono_in", PDMA_FILTER_PARAM(LOWEST, 9) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) { "pxa2xx-ac97", "pcm_pcm_aux_mono_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) PDMA_FILTER_PARAM(LOWEST, 10) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) { "pxa2xx-ac97", "pcm_pcm_stereo_in", PDMA_FILTER_PARAM(LOWEST, 11) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) { "pxa2xx-ac97", "pcm_pcm_stereo_out", PDMA_FILTER_PARAM(LOWEST, 12) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) { "pxa-ssp-dai.0", "rx", PDMA_FILTER_PARAM(LOWEST, 13) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) { "pxa-ssp-dai.0", "tx", PDMA_FILTER_PARAM(LOWEST, 14) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) { "pxa-ssp-dai.1", "rx", PDMA_FILTER_PARAM(LOWEST, 15) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) { "pxa-ssp-dai.1", "tx", PDMA_FILTER_PARAM(LOWEST, 16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) { "pxa2xx-ir", "rx", PDMA_FILTER_PARAM(LOWEST, 17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) { "pxa2xx-ir", "tx", PDMA_FILTER_PARAM(LOWEST, 18) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) { "pxa2xx-mci.0", "rx", PDMA_FILTER_PARAM(LOWEST, 21) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) { "pxa2xx-mci.0", "tx", PDMA_FILTER_PARAM(LOWEST, 22) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) { "pxa-ssp-dai.2", "rx", PDMA_FILTER_PARAM(LOWEST, 66) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) { "pxa-ssp-dai.2", "tx", PDMA_FILTER_PARAM(LOWEST, 67) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* PXA27x specific map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) { "pxa2xx-i2s", "rx", PDMA_FILTER_PARAM(LOWEST, 2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) { "pxa2xx-i2s", "tx", PDMA_FILTER_PARAM(LOWEST, 3) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) { "pxa27x-camera.0", "CI_Y", PDMA_FILTER_PARAM(HIGHEST, 68) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) { "pxa27x-camera.0", "CI_U", PDMA_FILTER_PARAM(HIGHEST, 69) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) { "pxa27x-camera.0", "CI_V", PDMA_FILTER_PARAM(HIGHEST, 70) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static struct mmp_dma_platdata pxa27x_dma_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .dma_channels = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .nb_requestors = 75,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .slave_map = pxa27x_slave_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .slave_map_cnt = ARRAY_SIZE(pxa27x_slave_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static int __init pxa27x_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (cpu_is_pxa27x()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) reset_status = RCSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) pxa27x_init_pm();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) register_syscore_ops(&pxa_irq_syscore_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) register_syscore_ops(&pxa2xx_mfp_syscore_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (!of_have_populated_dt()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) pxa_register_device(&pxa27x_device_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) &pxa27x_gpio_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) pxa2xx_set_dmac_info(&pxa27x_dma_pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ret = platform_add_devices(devices,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ARRAY_SIZE(devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) postcore_initcall(pxa27x_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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