Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #ifndef _ASM_ARCH_PXA27X_UDC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #define _ASM_ARCH_PXA27X_UDC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #ifdef _ASM_ARCH_PXA25X_UDC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #error You cannot include both PXA25x and PXA27x UDC support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define UDCCR           __REG(0x40600000) /* UDC Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define UDCCR_OEN	(1 << 31)	/* On-the-Go Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define UDCCR_AALTHNP	(1 << 30)	/* A-device Alternate Host Negotiation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 					   Protocol Port Support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define UDCCR_AHNP	(1 << 29)	/* A-device Host Negotiation Protocol
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 					   Support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define UDCCR_BHNP	(1 << 28)	/* B-device Host Negotiation Protocol
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 					   Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define UDCCR_DWRE	(1 << 16)	/* Device Remote Wake-up Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define UDCCR_ACN	(0x03 << 11)	/* Active UDC configuration Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define UDCCR_ACN_S	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define UDCCR_AIN	(0x07 << 8)	/* Active UDC interface Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define UDCCR_AIN_S	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define UDCCR_AAISN	(0x07 << 5)	/* Active UDC Alternate Interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 					   Setting Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define UDCCR_AAISN_S	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define UDCCR_SMAC	(1 << 4)	/* Switch Endpoint Memory to Active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 					   Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define UDCCR_EMCE	(1 << 3)	/* Endpoint Memory Configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 					   Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define UDCCR_UDR	(1 << 2)	/* UDC Resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define UDCCR_UDA	(1 << 1)	/* UDC Active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define UDCCR_UDE	(1 << 0)	/* UDC Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define UDCICR0         __REG(0x40600004) /* UDC Interrupt Control Register0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define UDCICR1         __REG(0x40600008) /* UDC Interrupt Control Register1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define UDCICR_FIFOERR	(1 << 1)	/* FIFO Error interrupt for EP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define UDCICR_PKTCOMPL (1 << 0)	/* Packet Complete interrupt for EP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define UDC_INT_FIFOERROR  (0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define UDC_INT_PACKETCMP  (0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define UDCICR1_IECC	(1 << 31)	/* IntEn - Configuration Change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define UDCICR1_IESOF	(1 << 30)	/* IntEn - Start of Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define UDCICR1_IERU	(1 << 29)	/* IntEn - Resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define UDCICR1_IESU	(1 << 28)	/* IntEn - Suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define UDCICR1_IERS	(1 << 27)	/* IntEn - Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define UDCISR0         __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define UDCISR1         __REG(0x40600010) /* UDC Interrupt Status Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define UDCISR1_IRCC	(1 << 31)	/* IntReq - Configuration Change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define UDCISR1_IRSOF	(1 << 30)	/* IntReq - Start of Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define UDCISR1_IRRU	(1 << 29)	/* IntReq - Resume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define UDCISR1_IRSU	(1 << 28)	/* IntReq - Suspend */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define UDCISR1_IRRS	(1 << 27)	/* IntReq - Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define UDCFNR          __REG(0x40600014) /* UDC Frame Number Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define UDCOTGICR	__REG(0x40600018) /* UDC On-The-Go interrupt control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define UDCOTGICR_IESF	(1 << 24)	/* OTG SET_FEATURE command recvd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define UDCOTGICR_IEXR	(1 << 17)	/* Extra Transceiver Interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 					   Rising Edge Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define UDCOTGICR_IEXF	(1 << 16)	/* Extra Transceiver Interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 					   Falling Edge Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define UDCOTGICR_IEVV40R (1 << 9)	/* OTG Vbus Valid 4.0V Rising Edge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 					   Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define UDCOTGICR_IEVV40F (1 << 8)	/* OTG Vbus Valid 4.0V Falling Edge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 					   Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define UDCOTGICR_IEVV44R (1 << 7)	/* OTG Vbus Valid 4.4V Rising Edge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 					   Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define UDCOTGICR_IEVV44F (1 << 6)	/* OTG Vbus Valid 4.4V Falling Edge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 					   Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define UDCOTGICR_IESVR	(1 << 5)	/* OTG Session Valid Rising Edge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 					   Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define UDCOTGICR_IESVF	(1 << 4)	/* OTG Session Valid Falling Edge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 					   Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define UDCOTGICR_IESDR	(1 << 3)	/* OTG A-Device SRP Detect Rising
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 					   Edge Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define UDCOTGICR_IESDF	(1 << 2)	/* OTG A-Device SRP Detect Falling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 					   Edge Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define UDCOTGICR_IEIDR	(1 << 1)	/* OTG ID Change Rising Edge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 					   Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define UDCOTGICR_IEIDF	(1 << 0)	/* OTG ID Change Falling Edge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 					   Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define UP2OCR		  __REG(0x40600020)  /* USB Port 2 Output Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define UP3OCR		  __REG(0x40600024)  /* USB Port 2 Output Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define UP2OCR_CPVEN	(1 << 0)	/* Charge Pump Vbus Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define UP2OCR_CPVPE	(1 << 1)	/* Charge Pump Vbus Pulse Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define UP2OCR_DPPDE	(1 << 2)	/* Host Port 2 Transceiver D+ Pull Down Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define UP2OCR_DMPDE	(1 << 3)	/* Host Port 2 Transceiver D- Pull Down Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define UP2OCR_DPPUE	(1 << 4)	/* Host Port 2 Transceiver D+ Pull Up Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define UP2OCR_DMPUE	(1 << 5)	/* Host Port 2 Transceiver D- Pull Up Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define UP2OCR_DPPUBE	(1 << 6)	/* Host Port 2 Transceiver D+ Pull Up Bypass Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define UP2OCR_DMPUBE	(1 << 7)	/* Host Port 2 Transceiver D- Pull Up Bypass Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define UP2OCR_EXSP		(1 << 8)	/* External Transceiver Speed Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define UP2OCR_EXSUS	(1 << 9)	/* External Transceiver Speed Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define UP2OCR_IDON		(1 << 10)	/* OTG ID Read Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define UP2OCR_HXS		(1 << 16)	/* Host Port 2 Transceiver Output Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define UP2OCR_HXOE		(1 << 17)	/* Host Port 2 Transceiver Output Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define UP2OCR_SEOS(x)		((x & 7) << 24)	/* Single-Ended Output Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define UDCCSN(x)	__REG2(0x40600100, (x) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define UDCCSR0         __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define UDCCSR0_SA	(1 << 7)	/* Setup Active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define UDCCSR0_RNE	(1 << 6)	/* Receive FIFO Not Empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define UDCCSR0_FST	(1 << 5)	/* Force Stall */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define UDCCSR0_SST	(1 << 4)	/* Sent Stall */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define UDCCSR0_DME	(1 << 3)	/* DMA Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define UDCCSR0_FTF	(1 << 2)	/* Flush Transmit FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define UDCCSR0_IPR	(1 << 1)	/* IN Packet Ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define UDCCSR0_OPC	(1 << 0)	/* OUT Packet Complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define UDCCSRA         __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define UDCCSRB         __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define UDCCSRC         __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define UDCCSRD         __REG(0x40600110) /* UDC Control/Status register - Endpoint D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define UDCCSRE         __REG(0x40600114) /* UDC Control/Status register - Endpoint E */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define UDCCSRF         __REG(0x40600118) /* UDC Control/Status register - Endpoint F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define UDCCSRG         __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define UDCCSRH         __REG(0x40600120) /* UDC Control/Status register - Endpoint H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define UDCCSRI         __REG(0x40600124) /* UDC Control/Status register - Endpoint I */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define UDCCSRJ         __REG(0x40600128) /* UDC Control/Status register - Endpoint J */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define UDCCSRK         __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define UDCCSRL         __REG(0x40600130) /* UDC Control/Status register - Endpoint L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define UDCCSRM         __REG(0x40600134) /* UDC Control/Status register - Endpoint M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define UDCCSRN         __REG(0x40600138) /* UDC Control/Status register - Endpoint N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define UDCCSRP         __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define UDCCSRQ         __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define UDCCSRR         __REG(0x40600144) /* UDC Control/Status register - Endpoint R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define UDCCSRS         __REG(0x40600148) /* UDC Control/Status register - Endpoint S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define UDCCSRT         __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define UDCCSRU         __REG(0x40600150) /* UDC Control/Status register - Endpoint U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define UDCCSRV         __REG(0x40600154) /* UDC Control/Status register - Endpoint V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define UDCCSRW         __REG(0x40600158) /* UDC Control/Status register - Endpoint W */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define UDCCSRX         __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define UDCCSR_DPE	(1 << 9)	/* Data Packet Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define UDCCSR_FEF	(1 << 8)	/* Flush Endpoint FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define UDCCSR_SP	(1 << 7)	/* Short Packet Control/Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define UDCCSR_BNE	(1 << 6)	/* Buffer Not Empty (IN endpoints) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define UDCCSR_BNF	(1 << 6)	/* Buffer Not Full (OUT endpoints) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define UDCCSR_FST	(1 << 5)	/* Force STALL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define UDCCSR_SST	(1 << 4)	/* Sent STALL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define UDCCSR_DME	(1 << 3)	/* DMA Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define UDCCSR_TRN	(1 << 2)	/* Tx/Rx NAK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define UDCCSR_PC	(1 << 1)	/* Packet Complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define UDCCSR_FS	(1 << 0)	/* FIFO needs service */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define UDCBCN(x)	__REG2(0x40600200, (x)<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define UDCBCR0         __REG(0x40600200) /* Byte Count Register - EP0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define UDCBCRA         __REG(0x40600204) /* Byte Count Register - EPA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define UDCBCRB         __REG(0x40600208) /* Byte Count Register - EPB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define UDCBCRC         __REG(0x4060020C) /* Byte Count Register - EPC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define UDCBCRD         __REG(0x40600210) /* Byte Count Register - EPD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define UDCBCRE         __REG(0x40600214) /* Byte Count Register - EPE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define UDCBCRF         __REG(0x40600218) /* Byte Count Register - EPF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define UDCBCRG         __REG(0x4060021C) /* Byte Count Register - EPG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define UDCBCRH         __REG(0x40600220) /* Byte Count Register - EPH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define UDCBCRI         __REG(0x40600224) /* Byte Count Register - EPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define UDCBCRJ         __REG(0x40600228) /* Byte Count Register - EPJ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define UDCBCRK         __REG(0x4060022C) /* Byte Count Register - EPK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define UDCBCRL         __REG(0x40600230) /* Byte Count Register - EPL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define UDCBCRM         __REG(0x40600234) /* Byte Count Register - EPM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define UDCBCRN         __REG(0x40600238) /* Byte Count Register - EPN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define UDCBCRP         __REG(0x4060023C) /* Byte Count Register - EPP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define UDCBCRQ         __REG(0x40600240) /* Byte Count Register - EPQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define UDCBCRR         __REG(0x40600244) /* Byte Count Register - EPR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define UDCBCRS         __REG(0x40600248) /* Byte Count Register - EPS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define UDCBCRT         __REG(0x4060024C) /* Byte Count Register - EPT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define UDCBCRU         __REG(0x40600250) /* Byte Count Register - EPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define UDCBCRV         __REG(0x40600254) /* Byte Count Register - EPV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define UDCBCRW         __REG(0x40600258) /* Byte Count Register - EPW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define UDCBCRX         __REG(0x4060025C) /* Byte Count Register - EPX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define UDCDN(x)	__REG2(0x40600300, (x)<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define PHYS_UDCDN(x)	(0x40600300 + ((x)<<2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define PUDCDN(x)	(volatile u32 *)(io_p2v(PHYS_UDCDN((x))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define UDCDR0          __REG(0x40600300) /* Data Register - EP0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define UDCDRA          __REG(0x40600304) /* Data Register - EPA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define UDCDRB          __REG(0x40600308) /* Data Register - EPB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define UDCDRC          __REG(0x4060030C) /* Data Register - EPC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define UDCDRD          __REG(0x40600310) /* Data Register - EPD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define UDCDRE          __REG(0x40600314) /* Data Register - EPE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define UDCDRF          __REG(0x40600318) /* Data Register - EPF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define UDCDRG          __REG(0x4060031C) /* Data Register - EPG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define UDCDRH          __REG(0x40600320) /* Data Register - EPH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define UDCDRI          __REG(0x40600324) /* Data Register - EPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define UDCDRJ          __REG(0x40600328) /* Data Register - EPJ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define UDCDRK          __REG(0x4060032C) /* Data Register - EPK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define UDCDRL          __REG(0x40600330) /* Data Register - EPL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define UDCDRM          __REG(0x40600334) /* Data Register - EPM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define UDCDRN          __REG(0x40600338) /* Data Register - EPN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define UDCDRP          __REG(0x4060033C) /* Data Register - EPP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define UDCDRQ          __REG(0x40600340) /* Data Register - EPQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define UDCDRR          __REG(0x40600344) /* Data Register - EPR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define UDCDRS          __REG(0x40600348) /* Data Register - EPS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define UDCDRT          __REG(0x4060034C) /* Data Register - EPT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define UDCDRU          __REG(0x40600350) /* Data Register - EPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define UDCDRV          __REG(0x40600354) /* Data Register - EPV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define UDCDRW          __REG(0x40600358) /* Data Register - EPW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define UDCDRX          __REG(0x4060035C) /* Data Register - EPX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define UDCCN(x)       __REG2(0x40600400, (x)<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define UDCCRA          __REG(0x40600404) /* Configuration register EPA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define UDCCRB          __REG(0x40600408) /* Configuration register EPB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define UDCCRC          __REG(0x4060040C) /* Configuration register EPC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define UDCCRD          __REG(0x40600410) /* Configuration register EPD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define UDCCRE          __REG(0x40600414) /* Configuration register EPE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define UDCCRF          __REG(0x40600418) /* Configuration register EPF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define UDCCRG          __REG(0x4060041C) /* Configuration register EPG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define UDCCRH          __REG(0x40600420) /* Configuration register EPH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define UDCCRI          __REG(0x40600424) /* Configuration register EPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define UDCCRJ          __REG(0x40600428) /* Configuration register EPJ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define UDCCRK          __REG(0x4060042C) /* Configuration register EPK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define UDCCRL          __REG(0x40600430) /* Configuration register EPL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define UDCCRM          __REG(0x40600434) /* Configuration register EPM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define UDCCRN          __REG(0x40600438) /* Configuration register EPN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define UDCCRP          __REG(0x4060043C) /* Configuration register EPP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define UDCCRQ          __REG(0x40600440) /* Configuration register EPQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define UDCCRR          __REG(0x40600444) /* Configuration register EPR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define UDCCRS          __REG(0x40600448) /* Configuration register EPS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define UDCCRT          __REG(0x4060044C) /* Configuration register EPT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define UDCCRU          __REG(0x40600450) /* Configuration register EPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define UDCCRV          __REG(0x40600454) /* Configuration register EPV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define UDCCRW          __REG(0x40600458) /* Configuration register EPW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define UDCCRX          __REG(0x4060045C) /* Configuration register EPX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define UDCCONR_CN	(0x03 << 25)	/* Configuration Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define UDCCONR_CN_S	(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define UDCCONR_IN	(0x07 << 22)	/* Interface Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define UDCCONR_IN_S	(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define UDCCONR_AISN	(0x07 << 19)	/* Alternate Interface Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define UDCCONR_AISN_S	(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define UDCCONR_EN	(0x0f << 15)	/* Endpoint Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define UDCCONR_EN_S	(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define UDCCONR_ET	(0x03 << 13)	/* Endpoint Type: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define UDCCONR_ET_S	(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define UDCCONR_ET_INT	(0x03 << 13)	/*   Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define UDCCONR_ET_BULK	(0x02 << 13)	/*   Bulk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define UDCCONR_ET_ISO	(0x01 << 13)	/*   Isochronous */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define UDCCONR_ET_NU	(0x00 << 13)	/*   Not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define UDCCONR_ED	(1 << 12)	/* Endpoint Direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define UDCCONR_MPS	(0x3ff << 2)	/* Maximum Packet Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define UDCCONR_MPS_S	(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define UDCCONR_DE	(1 << 1)	/* Double Buffering Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define UDCCONR_EE	(1 << 0)	/* Endpoint Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define UDC_INT_FIFOERROR  (0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define UDC_INT_PACKETCMP  (0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define UDC_FNR_MASK     (0x7ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define UDCCSR_WR_MASK   (UDCCSR_DME|UDCCSR_FST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define UDC_BCR_MASK    (0x3ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #endif