Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  linux/arch/arm/mach-pxa/pxa25x.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Author:	Nicolas Pitre
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *  Created:	Jun 15, 2001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  Copyright:	MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Code specific to PXA21x/25x/26x variants.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Since this file should be linked before any other machine specific file,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * the __initcall() here will be executed first.  This serves as default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * initialization stuff for PXA machines which can be overridden later if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * need be.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/dma/pxa-dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/gpio-pxa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <linux/irqchip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <linux/platform_data/mmp_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <asm/suspend.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include <mach/irqs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #include "pxa25x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #include <mach/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #include "pm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #include <mach/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #include <mach/smemc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #include "generic.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #include "devices.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  * Various clock factors driven by the CCCR register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define SAVE(x)		sleep_save[SLEEP_SAVE_##x] = x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define RESTORE(x)	x = sleep_save[SLEEP_SAVE_##x]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  * List of global PXA peripheral registers to preserve.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  * More ones like CP and general purpose register values are preserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  * with the stack pointer in sleep.S.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	SLEEP_SAVE_PSTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	SLEEP_SAVE_COUNT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) static void pxa25x_cpu_pm_save(unsigned long *sleep_save)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	SAVE(PSTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	RESTORE(PSTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static void pxa25x_cpu_pm_enter(suspend_state_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	/* Clear reset status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	switch (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	case PM_SUSPEND_MEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		cpu_suspend(PWRMODE_SLEEP, pxa25x_finish_suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) static int pxa25x_cpu_pm_prepare(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	/* set resume return address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	PSPR = __pa_symbol(cpu_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) static void pxa25x_cpu_pm_finish(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	/* ensure not to come back here if it wasn't intended */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	PSPR = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	.save_count	= SLEEP_SAVE_COUNT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	.valid		= suspend_valid_only_mem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	.save		= pxa25x_cpu_pm_save,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	.restore	= pxa25x_cpu_pm_restore,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	.enter		= pxa25x_cpu_pm_enter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	.prepare	= pxa25x_cpu_pm_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	.finish		= pxa25x_cpu_pm_finish,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static void __init pxa25x_init_pm(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	pxa_cpu_pm_fns = &pxa25x_cpu_pm_fns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static inline void pxa25x_init_pm(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int pxa25x_set_wake(struct irq_data *d, unsigned int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	int gpio = pxa_irq_to_gpio(d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	uint32_t mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	if (gpio >= 0 && gpio < 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		return gpio_set_wake(gpio, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	if (d->irq == IRQ_RTCAlrm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		mask = PWER_RTC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		goto set_pwer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) set_pwer:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		PWER |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		PWER &=~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) void __init pxa25x_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	pxa_init_irq(32, pxa25x_set_wake);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #ifdef CONFIG_CPU_PXA26x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) void __init pxa26x_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	pxa_init_irq(32, pxa25x_set_wake);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int __init __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) pxa25x_dt_init_irq(struct device_node *node, struct device_node *parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	pxa_dt_irq_init(pxa25x_set_wake);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	set_handle_irq(icip_handle_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) IRQCHIP_DECLARE(pxa25x_intc, "marvell,pxa-intc", pxa25x_dt_init_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static struct map_desc pxa25x_io_desc[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	{	/* Mem Ctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		.virtual	= (unsigned long)SMEMC_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		.pfn		= __phys_to_pfn(PXA2XX_SMEMC_BASE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		.length		= SMEMC_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		.type		= MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	}, {	/* UNCACHED_PHYS_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		.virtual	= UNCACHED_PHYS_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		.pfn		= __phys_to_pfn(0x00000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		.length		= UNCACHED_PHYS_0_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		.type		= MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) void __init pxa25x_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	pxa_map_io();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	iotable_init(ARRAY_AND_SIZE(pxa25x_io_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	pxa25x_get_clk_frequency_khz(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static struct pxa_gpio_platform_data pxa25x_gpio_info __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	.irq_base	= PXA_GPIO_TO_IRQ(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	.gpio_set_wake	= gpio_set_wake,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static struct platform_device *pxa25x_devices[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	&pxa25x_device_udc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	&pxa_device_pmu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	&pxa_device_i2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	&sa1100_device_rtc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	&pxa25x_device_ssp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	&pxa25x_device_nssp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	&pxa25x_device_assp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	&pxa25x_device_pwm0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	&pxa25x_device_pwm1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	&pxa_device_asoc_platform,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static const struct dma_slave_map pxa25x_slave_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	/* PXA25x, PXA27x and PXA3xx common entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	{ "pxa2xx-ac97", "pcm_pcm_mic_mono", PDMA_FILTER_PARAM(LOWEST, 8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	{ "pxa2xx-ac97", "pcm_pcm_aux_mono_in", PDMA_FILTER_PARAM(LOWEST, 9) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	{ "pxa2xx-ac97", "pcm_pcm_aux_mono_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	  PDMA_FILTER_PARAM(LOWEST, 10) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	{ "pxa2xx-ac97", "pcm_pcm_stereo_in", PDMA_FILTER_PARAM(LOWEST, 11) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	{ "pxa2xx-ac97", "pcm_pcm_stereo_out", PDMA_FILTER_PARAM(LOWEST, 12) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	{ "pxa-ssp-dai.1", "rx", PDMA_FILTER_PARAM(LOWEST, 13) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	{ "pxa-ssp-dai.1", "tx", PDMA_FILTER_PARAM(LOWEST, 14) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	{ "pxa-ssp-dai.2", "rx", PDMA_FILTER_PARAM(LOWEST, 15) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	{ "pxa-ssp-dai.2", "tx", PDMA_FILTER_PARAM(LOWEST, 16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	{ "pxa2xx-ir", "rx", PDMA_FILTER_PARAM(LOWEST, 17) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	{ "pxa2xx-ir", "tx", PDMA_FILTER_PARAM(LOWEST, 18) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	{ "pxa2xx-mci.0", "rx", PDMA_FILTER_PARAM(LOWEST, 21) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	{ "pxa2xx-mci.0", "tx", PDMA_FILTER_PARAM(LOWEST, 22) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	/* PXA25x specific map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	{ "pxa25x-ssp.0", "rx", PDMA_FILTER_PARAM(LOWEST, 13) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	{ "pxa25x-ssp.0", "tx", PDMA_FILTER_PARAM(LOWEST, 14) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	{ "pxa25x-nssp.1", "rx", PDMA_FILTER_PARAM(LOWEST, 15) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	{ "pxa25x-nssp.1", "tx", PDMA_FILTER_PARAM(LOWEST, 16) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	{ "pxa25x-nssp.2", "rx", PDMA_FILTER_PARAM(LOWEST, 23) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	{ "pxa25x-nssp.2", "tx", PDMA_FILTER_PARAM(LOWEST, 24) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static struct mmp_dma_platdata pxa25x_dma_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	.dma_channels	= 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	.nb_requestors	= 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	.slave_map	= pxa25x_slave_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	.slave_map_cnt	= ARRAY_SIZE(pxa25x_slave_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static int __init pxa25x_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	if (cpu_is_pxa25x()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		reset_status = RCSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		pxa25x_init_pm();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		register_syscore_ops(&pxa_irq_syscore_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		register_syscore_ops(&pxa2xx_mfp_syscore_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		if (!of_have_populated_dt()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 			pxa2xx_set_dmac_info(&pxa25x_dma_pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 			pxa_register_device(&pxa25x_device_gpio, &pxa25x_gpio_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 			ret = platform_add_devices(pxa25x_devices,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 						   ARRAY_SIZE(pxa25x_devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) postcore_initcall(pxa25x_init);