Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * arch/arm/mach-pxa/include/mach/pcm990_baseboard.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * (c) 2003 Phytec Messtechnik GmbH <armlinux@phytec.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * (c) 2007 Juergen Beisert <j.beisert@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include "pcm027.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <mach/irqs.h> /* PXA_GPIO_TO_IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * definitions relevant only when the PCM-990
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * development base board is in use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) /* CPLD's interrupt controller is connected to PCM-027 GPIO 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define PCM990_CTRL_INT_IRQ_GPIO	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define PCM990_CTRL_INT_IRQ		PXA_GPIO_TO_IRQ(PCM990_CTRL_INT_IRQ_GPIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define PCM990_CTRL_INT_IRQ_EDGE	IRQ_TYPE_EDGE_RISING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define PCM990_CTRL_PHYS		PXA_CS1_PHYS	/* 16-Bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define PCM990_CTRL_SIZE		(1*1024*1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define PCM990_CTRL_PWR_IRQ_GPIO	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define PCM990_CTRL_PWR_IRQ		PXA_GPIO_TO_IRQ(PCM990_CTRL_PWR_IRQ_GPIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define PCM990_CTRL_PWR_IRQ_EDGE	IRQ_TYPE_EDGE_RISING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* visible CPLD (U7) registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define PCM990_CTRL_REG0	0x0000	/* RESET REGISTER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define PCM990_CTRL_SYSRES	0x0001	/* System RESET REGISTER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define PCM990_CTRL_RESOUT	0x0002	/* RESETOUT Enable REGISTER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define PCM990_CTRL_RESGPIO	0x0004	/* RESETGPIO Enable REGISTER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define PCM990_CTRL_REG1	0x0002	/* Power REGISTER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define PCM990_CTRL_5VOFF	0x0001	/* Disable  5V Regulators */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define PCM990_CTRL_CANPWR	0x0004	/* Enable CANPWR ADUM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define PCM990_CTRL_PM_5V	0x0008	/* Read 5V OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define PCM990_CTRL_REG2	0x0004	/* LED REGISTER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define PCM990_CTRL_LEDPWR	0x0001	/* POWER LED enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define PCM990_CTRL_LEDBAS	0x0002	/* BASIS LED enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define PCM990_CTRL_LEDUSR	0x0004	/* USER LED enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define PCM990_CTRL_REG3	0x0006	/* LCD CTRL REGISTER 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define PCM990_CTRL_LCDPWR	0x0001	/* RW LCD Power on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define PCM990_CTRL_LCDON	0x0002	/* RW LCD Latch on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define PCM990_CTRL_LCDPOS1	0x0004	/* RW POS 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define PCM990_CTRL_LCDPOS2	0x0008	/* RW POS 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define PCM990_CTRL_REG4	0x0008	/* MMC1 CTRL REGISTER 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define PCM990_CTRL_MMC1PWR	0x0001 /* RW MMC1 Power on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define PCM990_CTRL_REG5	0x000A	/* MMC2 CTRL REGISTER 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define PCM990_CTRL_MMC2PWR	0x0001	/* RW MMC2 Power on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define PCM990_CTRL_MMC2LED	0x0002	/* RW MMC2 LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define PCM990_CTRL_MMC2DE	0x0004	/* R MMC2 Card detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define PCM990_CTRL_MMC2WP	0x0008	/* R MMC2 Card write protect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define PCM990_CTRL_INTSETCLR	0x000C	/* Interrupt Clear REGISTER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define PCM990_CTRL_INTC0	0x0001	/* Clear Reg BT Detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define PCM990_CTRL_INTC1	0x0002	/* Clear Reg FR RI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define PCM990_CTRL_INTC2	0x0004	/* Clear Reg MMC1 Detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define PCM990_CTRL_INTC3	0x0008	/* Clear Reg PM_5V off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define PCM990_CTRL_INTMSKENA	0x000E	/* Interrupt Enable REGISTER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define PCM990_CTRL_ENAINT0	0x0001	/* Enable Int BT Detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define PCM990_CTRL_ENAINT1	0x0002	/* Enable Int FR RI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define PCM990_CTRL_ENAINT2	0x0004	/* Enable Int MMC1 Detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define PCM990_CTRL_ENAINT3	0x0008	/* Enable Int PM_5V off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define PCM990_CTRL_REG8	0x0014	/* Uart REGISTER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define PCM990_CTRL_FFSD	0x0001	/* BT Uart Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define PCM990_CTRL_BTSD	0x0002	/* FF Uart Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define PCM990_CTRL_FFRI	0x0004	/* FF Uart RI detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define PCM990_CTRL_BTRX	0x0008	/* BT Uart Rx detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define PCM990_CTRL_REG9	0x0010	/* AC97 Flash REGISTER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define PCM990_CTRL_FLWP	0x0001	/* pC Flash Write Protect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define PCM990_CTRL_FLDIS	0x0002	/* pC Flash Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define PCM990_CTRL_AC97ENA	0x0004	/* Enable AC97 Expansion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define PCM990_CTRL_REG10	0x0012	/* GPS-REGISTER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define PCM990_CTRL_GPSPWR	0x0004	/* GPS-Modul Power on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define PCM990_CTRL_GPSENA	0x0008	/* GPS-Modul Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define PCM990_CTRL_REG11	0x0014	/* Accu REGISTER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define PCM990_CTRL_ACENA	0x0001	/* Charge Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define PCM990_CTRL_ACSEL	0x0002	/* Charge Akku -> DC Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define PCM990_CTRL_ACPRES	0x0004	/* DC Present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define PCM990_CTRL_ACALARM	0x0008	/* Error Akku */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93)  * IDE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define PCM990_IDE_IRQ_GPIO	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define PCM990_IDE_IRQ		PXA_GPIO_TO_IRQ(PCM990_IDE_IRQ_GPIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define PCM990_IDE_IRQ_EDGE	IRQ_TYPE_EDGE_RISING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define PCM990_IDE_PLD_PHYS	0x20000000	/* 16 bit wide */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define PCM990_IDE_PLD_BASE	0xee000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PCM990_IDE_PLD_SIZE	(1*1024*1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* visible CPLD (U6) registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PCM990_IDE_PLD_REG0	0x1000	/* OFFSET IDE REGISTER 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PCM990_IDE_PM5V		0x0004	/* R System VCC_5V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PCM990_IDE_STBY		0x0008	/* R System StandBy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PCM990_IDE_PLD_REG1	0x1002	/* OFFSET IDE REGISTER 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PCM990_IDE_IDEMODE	0x0001	/* R TrueIDE Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PCM990_IDE_DMAENA	0x0004	/* RW DMA Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PCM990_IDE_DMA1_0	0x0008	/* RW 1=DREQ1 0=DREQ0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PCM990_IDE_PLD_REG2	0x1004	/* OFFSET IDE REGISTER 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PCM990_IDE_RESENA	0x0001	/* RW IDE Reset Bit enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PCM990_IDE_RES		0x0002	/* RW IDE Reset Bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PCM990_IDE_RDY		0x0008	/* RDY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PCM990_IDE_PLD_REG3	0x1006	/* OFFSET IDE REGISTER 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PCM990_IDE_IDEOE	0x0001	/* RW Latch on Databus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PCM990_IDE_IDEON	0x0002	/* RW Latch on Control Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PCM990_IDE_IDEIN	0x0004	/* RW Latch on Interrupt usw. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PCM990_IDE_PLD_REG4	0x1008	/* OFFSET IDE REGISTER 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PCM990_IDE_PWRENA	0x0001	/* RW IDE Power enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PCM990_IDE_5V		0x0002	/* R IDE Power 5V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PCM990_IDE_PWG		0x0008	/* R IDE Power is on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PCM990_IDE_PLD_P2V(x) ((x) - PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_BASE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PCM990_IDE_PLD_V2P(x) ((x) - PCM990_IDE_PLD_BASE + PCM990_IDE_PLD_PHYS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)  * Compact Flash
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define PCM990_CF_IRQ_GPIO	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PCM990_CF_IRQ		PXA_GPIO_TO_IRQ(PCM990_CF_IRQ_GPIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PCM990_CF_IRQ_EDGE	IRQ_TYPE_EDGE_RISING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PCM990_CF_CD_GPIO	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PCM990_CF_CD		PXA_GPIO_TO_IRQ(PCM990_CF_CD_GPIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PCM990_CF_CD_EDGE	IRQ_TYPE_EDGE_RISING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PCM990_CF_PLD_PHYS	0x30000000	/* 16 bit wide */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* visible CPLD (U6) registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define PCM990_CF_PLD_REG0	0x1000	/* OFFSET CF REGISTER 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define PCM990_CF_REG0_LED	0x0001	/* RW LED on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define PCM990_CF_REG0_BLK	0x0002	/* RW LED flash when access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define PCM990_CF_REG0_PM5V	0x0004	/* R System VCC_5V enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PCM990_CF_REG0_STBY	0x0008	/* R System StandBy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PCM990_CF_PLD_REG1	0x1002	/* OFFSET CF REGISTER 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define PCM990_CF_REG1_IDEMODE	0x0001	/* RW CF card run as TrueIDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define PCM990_CF_REG1_CF0	0x0002	/* RW CF card at ADDR 0x28000000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define PCM990_CF_PLD_REG2	0x1004	/* OFFSET CF REGISTER 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define PCM990_CF_REG2_RES	0x0002	/* RW CF RESET BIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define PCM990_CF_REG2_RDYENA	0x0004	/* RW Enable CF_RDY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define PCM990_CF_REG2_RDY	0x0008	/* R CF_RDY auf PWAIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define PCM990_CF_PLD_REG3	0x1006	/* OFFSET CF REGISTER 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define PCM990_CF_REG3_CFOE	0x0001	/* RW Latch on Databus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define PCM990_CF_REG3_CFON	0x0002	/* RW Latch on Control Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define PCM990_CF_REG3_CFIN	0x0004	/* RW Latch on Interrupt usw. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define PCM990_CF_REG3_CFCD	0x0008	/* RW Latch on CD1/2 VS1/2 usw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define PCM990_CF_PLD_REG4	0x1008	/* OFFSET CF REGISTER 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define PCM990_CF_REG4_PWRENA	0x0001	/* RW CF Power on (CD1/2 = "00") */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define PCM990_CF_REG4_5_3V	0x0002	/* RW 1 = 5V CF_VCC 0 = 3 V CF_VCC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define PCM990_CF_REG4_3B	0x0004	/* RW 3.0V Backup from VCC (5_3V=0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define PCM990_CF_REG4_PWG	0x0008	/* R CF-Power is on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define PCM990_CF_PLD_REG5	0x100A	/* OFFSET CF REGISTER 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define PCM990_CF_REG5_BVD1	0x0001	/* R CF /BVD1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define PCM990_CF_REG5_BVD2	0x0002	/* R CF /BVD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define PCM990_CF_REG5_VS1	0x0004	/* R CF /VS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define PCM990_CF_REG5_VS2	0x0008	/* R CF /VS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define PCM990_CF_PLD_REG6	0x100C	/* OFFSET CF REGISTER 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define PCM990_CF_REG6_CD1	0x0001	/* R CF Card_Detect1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define PCM990_CF_REG6_CD2	0x0002	/* R CF Card_Detect2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)  * Wolfson AC97 Touch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define PCM990_AC97_IRQ_GPIO	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define PCM990_AC97_IRQ		PXA_GPIO_TO_IRQ(PCM990_AC97_IRQ_GPIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define PCM990_AC97_IRQ_EDGE	IRQ_TYPE_EDGE_RISING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)  * MMC phyCORE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define PCM990_MMC0_IRQ_GPIO	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define PCM990_MMC0_IRQ		PXA_GPIO_TO_IRQ(PCM990_MMC0_IRQ_GPIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define PCM990_MMC0_IRQ_EDGE	IRQ_TYPE_EDGE_FALLING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)  * USB phyCore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define PCM990_USB_OVERCURRENT (88 | GPIO_ALT_FN_1_IN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define PCM990_USB_PWR_EN (89 | GPIO_ALT_FN_2_OUT)