Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  arch/arm/mach-pxa/pcm990-baseboard.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *  Support for the Phytec phyCORE-PXA270 Development Platform (PCM-990).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *  Refer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *   http://www.phytec.com/products/rdk/ARM-XScale/phyCORE-XScale-PXA270.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *  for additional hardware info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *  Author:	Juergen Kilb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *  Created:	April 05, 2005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *  Copyright:	Phytec Messtechnik GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *  e-Mail:	armlinux@phytec.de
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *  based on Intel Mainstone Board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *  Copyright 2007 Juergen Beisert @ Pengutronix (j.beisert@pengutronix.de)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/platform_data/i2c-pxa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/pwm_backlight.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include "pxa27x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <mach/audio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <linux/platform_data/mmc-pxamci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <linux/platform_data/usb-ohci-pxa27x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include "pcm990_baseboard.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include <linux/platform_data/video-pxafb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #include "devices.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #include "generic.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) static unsigned long pcm990_pin_config[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	/* MMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	GPIO32_MMC_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	GPIO112_MMC_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	GPIO92_MMC_DAT_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	GPIO109_MMC_DAT_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	GPIO110_MMC_DAT_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	GPIO111_MMC_DAT_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	/* USB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	GPIO88_USBH1_PWR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	GPIO89_USBH1_PEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	/* PWM0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	GPIO16_PWM0_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	/* I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	GPIO117_I2C_SCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	GPIO118_I2C_SDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	/* AC97 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	GPIO28_AC97_BITCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	GPIO29_AC97_SDATA_IN_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	GPIO30_AC97_SDATA_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	GPIO31_AC97_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) static void __iomem *pcm990_cpld_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) static u8 pcm990_cpld_readb(unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	return readb(pcm990_cpld_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) static void pcm990_cpld_writeb(u8 value, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	writeb(value, pcm990_cpld_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  * pcm990_lcd_power - control power supply to the LCD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  * @on: 0 = switch off, 1 = switch on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  * Called by the pxafb driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #ifndef CONFIG_PCM990_DISPLAY_NONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) static void pcm990_lcd_power(int on, struct fb_var_screeninfo *var)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		/* enable LCD-Latches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		 * power on LCD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		pcm990_cpld_writeb(PCM990_CTRL_LCDPWR + PCM990_CTRL_LCDON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 				PCM990_CTRL_REG3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		/* disable LCD-Latches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		 * power off LCD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		pcm990_cpld_writeb(0, PCM990_CTRL_REG3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #if defined(CONFIG_PCM990_DISPLAY_SHARP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static struct pxafb_mode_info fb_info_sharp_lq084v1dg21 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	.pixclock		= 28000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	.xres			= 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	.yres			= 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	.bpp			= 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	.hsync_len		= 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	.left_margin		= 103,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	.right_margin		= 47,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	.vsync_len		= 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	.upper_margin		= 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	.lower_margin		= 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	.sync			= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	.cmap_greyscale		= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static struct pxafb_mach_info pcm990_fbinfo __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	.modes			= &fb_info_sharp_lq084v1dg21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	.num_modes		= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	.lcd_conn		= LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	.pxafb_lcd_power	= pcm990_lcd_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #elif defined(CONFIG_PCM990_DISPLAY_NEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct pxafb_mode_info fb_info_nec_nl6448bc20_18d = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	.pixclock		= 39720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	.xres			= 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	.yres			= 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	.bpp			= 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	.hsync_len		= 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	.left_margin		= 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	.right_margin		= 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	.vsync_len		= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	.upper_margin		= 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	.lower_margin		= 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	.sync			= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	.cmap_greyscale		= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static struct pxafb_mach_info pcm990_fbinfo __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	.modes			= &fb_info_nec_nl6448bc20_18d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	.num_modes		= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	.lcd_conn		= LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	.pxafb_lcd_power	= pcm990_lcd_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static struct pwm_lookup pcm990_pwm_lookup[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	PWM_LOOKUP("pxa27x-pwm.0", 0, "pwm-backlight.0", NULL, 78770,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		   PWM_POLARITY_NORMAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static struct platform_pwm_backlight_data pcm990_backlight_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	.max_brightness	= 1023,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	.dft_brightness	= 1023,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static struct platform_device pcm990_backlight_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	.name		= "pwm-backlight",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	.dev		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		.parent = &pxa27x_device_pwm0.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		.platform_data = &pcm990_backlight_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)  * The PCM-990 development baseboard uses PCM-027's hardware in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)  * following way:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)  * - LCD support is in use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)  *  - GPIO16 is output for back light on/off with PWM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)  *  - GPIO58 ... GPIO73 are outputs for display data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)  *  - GPIO74 is output output for LCDFCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)  *  - GPIO75 is output for LCDLCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)  *  - GPIO76 is output for LCDPCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)  *  - GPIO77 is output for LCDBIAS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)  * - MMC support is in use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)  *  - GPIO32 is output for MMCCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)  *  - GPIO92 is MMDAT0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)  *  - GPIO109 is MMDAT1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)  *  - GPIO110 is MMCS0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)  *  - GPIO111 is MMCS1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)  *  - GPIO112 is MMCMD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)  * - IDE/CF card is in use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)  *  - GPIO48 is output /POE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)  *  - GPIO49 is output /PWE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)  *  - GPIO50 is output /PIOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)  *  - GPIO51 is output /PIOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)  *  - GPIO54 is output /PCE2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)  *  - GPIO55 is output /PREG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)  *  - GPIO56 is input /PWAIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)  *  - GPIO57 is output /PIOS16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)  *  - GPIO79 is output PSKTSEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)  *  - GPIO85 is output /PCE1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)  * - FFUART is in use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)  *  - GPIO34 is input FFRXD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)  *  - GPIO35 is input FFCTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)  *  - GPIO36 is input FFDCD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)  *  - GPIO37 is input FFDSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)  *  - GPIO38 is input FFRI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)  *  - GPIO39 is output FFTXD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)  *  - GPIO40 is output FFDTR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)  *  - GPIO41 is output FFRTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)  * - BTUART is in use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)  *  - GPIO42 is input BTRXD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)  *  - GPIO43 is output BTTXD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)  *  - GPIO44 is input BTCTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)  *  - GPIO45 is output BTRTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)  * - IRUART is in use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)  *  - GPIO46 is input STDRXD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)  *  - GPIO47 is output STDTXD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)  * - AC97 is in use*)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)  *  - GPIO28 is input AC97CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)  *  - GPIO29 is input AC97DatIn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)  *  - GPIO30 is output AC97DatO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)  *  - GPIO31 is output AC97SYNC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)  *  - GPIO113 is output AC97_RESET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)  * - SSP is in use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)  *  - GPIO23 is output SSPSCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)  *  - GPIO24 is output chip select to Max7301
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)  *  - GPIO25 is output SSPTXD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)  *  - GPIO26 is input SSPRXD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)  *  - GPIO27 is input for Max7301 IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)  *  - GPIO53 is input SSPSYSCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)  * - SSP3 is in use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)  *  - GPIO81 is output SSPTXD3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)  *  - GPIO82 is input SSPRXD3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)  *  - GPIO83 is output SSPSFRM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)  *  - GPIO84 is output SSPCLK3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)  * Otherwise claimed GPIOs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)  * GPIO1 -> IRQ from user switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)  * GPIO9 -> IRQ from power management
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)  * GPIO10 -> IRQ from WML9712 AC97 controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)  * GPIO11 -> IRQ from IDE controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)  * GPIO12 -> IRQ from CF controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)  * GPIO13 -> IRQ from CF controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)  * GPIO14 -> GPIO free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)  * GPIO15 -> /CS1 selects baseboard's Control CPLD (U7, 16 bit wide data path)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)  * GPIO19 -> GPIO free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)  * GPIO20 -> /SDCS2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)  * GPIO21 -> /CS3 PC card socket select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)  * GPIO33 -> /CS5  network controller select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)  * GPIO78 -> /CS2  (16 bit wide data path)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)  * GPIO80 -> /CS4  (16 bit wide data path)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)  * GPIO86 -> GPIO free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)  * GPIO87 -> GPIO free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)  * GPIO90 -> LED0 on CPU module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)  * GPIO91 -> LED1 on CPI module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)  * GPIO117 -> SCL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)  * GPIO118 -> SDA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static unsigned long pcm990_irq_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static void pcm990_mask_ack_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	int pcm990_irq = (d->irq - PCM027_IRQ(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	pcm990_irq_enabled &= ~(1 << pcm990_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	pcm990_cpld_writeb(pcm990_irq_enabled, PCM990_CTRL_INTMSKENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static void pcm990_unmask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	int pcm990_irq = (d->irq - PCM027_IRQ(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	/* the irq can be acknowledged only if deasserted, so it's done here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	pcm990_irq_enabled |= (1 << pcm990_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	val = pcm990_cpld_readb(PCM990_CTRL_INTSETCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	val |= 1 << pcm990_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	pcm990_cpld_writeb(val, PCM990_CTRL_INTSETCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	pcm990_cpld_writeb(pcm990_irq_enabled, PCM990_CTRL_INTMSKENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static struct irq_chip pcm990_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	.irq_mask_ack	= pcm990_mask_ack_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	.irq_unmask	= pcm990_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static void pcm990_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	unsigned long pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	pending = ~pcm990_cpld_readb(PCM990_CTRL_INTSETCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	pending &= pcm990_irq_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		/* clear our parent IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		desc->irq_data.chip->irq_ack(&desc->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		if (likely(pending)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 			irq = PCM027_IRQ(0) + __ffs(pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 			generic_handle_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		pending = ~pcm990_cpld_readb(PCM990_CTRL_INTSETCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		pending &= pcm990_irq_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	} while (pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static void __init pcm990_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	/* setup extra PCM990 irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	for (irq = PCM027_IRQ(0); irq <= PCM027_IRQ(3); irq++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		irq_set_chip_and_handler(irq, &pcm990_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 					 handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	/* disable all Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	pcm990_cpld_writeb(0x0, PCM990_CTRL_INTMSKENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	pcm990_cpld_writeb(0xff, PCM990_CTRL_INTSETCLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	irq_set_chained_handler(PCM990_CTRL_INT_IRQ, pcm990_irq_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	irq_set_irq_type(PCM990_CTRL_INT_IRQ, PCM990_CTRL_INT_IRQ_EDGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static int pcm990_mci_init(struct device *dev, irq_handler_t mci_detect_int,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 			void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	err = request_irq(PCM027_MMCDET_IRQ, mci_detect_int, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 			     "MMC card detect", data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		printk(KERN_ERR "pcm990_mci_init: MMC/SD: can't request MMC "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 				"card detect IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int pcm990_mci_setpower(struct device *dev, unsigned int vdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	struct pxamci_platform_data *p_d = dev->platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	val = pcm990_cpld_readb(PCM990_CTRL_REG5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	if ((1 << vdd) & p_d->ocr_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		val |= PCM990_CTRL_MMC2PWR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		val &= ~PCM990_CTRL_MMC2PWR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	pcm990_cpld_writeb(PCM990_CTRL_MMC2PWR, PCM990_CTRL_REG5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static void pcm990_mci_exit(struct device *dev, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	free_irq(PCM027_MMCDET_IRQ, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define MSECS_PER_JIFFY (1000/HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static struct pxamci_platform_data pcm990_mci_platform_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	.detect_delay_ms	= 250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	.ocr_mask		= MMC_VDD_32_33 | MMC_VDD_33_34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	.init 			= pcm990_mci_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	.setpower 		= pcm990_mci_setpower,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	.exit			= pcm990_mci_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static struct pxaohci_platform_data pcm990_ohci_platform_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	.port_mode	= PMM_PERPORT_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	.flags		= ENABLE_PORT1 | POWER_CONTROL_LOW | POWER_SENSE_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	.power_on_delay	= 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)  * system init for baseboard usage. Will be called by pcm027 init.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)  * Add platform devices present on this baseboard and init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)  * them from CPU side as far as required to use them later on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) void __init pcm990_baseboard_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	pxa2xx_mfp_config(ARRAY_AND_SIZE(pcm990_pin_config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	pcm990_cpld_base = ioremap(PCM990_CTRL_PHYS, PCM990_CTRL_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	if (!pcm990_cpld_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		pr_err("pcm990: failed to ioremap cpld\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	/* register CPLD's IRQ controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	pcm990_init_irq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #ifndef CONFIG_PCM990_DISPLAY_NONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	pxa_set_fb_info(NULL, &pcm990_fbinfo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	pwm_add_table(pcm990_pwm_lookup, ARRAY_SIZE(pcm990_pwm_lookup));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	platform_device_register(&pcm990_backlight_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	/* MMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	pxa_set_mci_info(&pcm990_mci_platform_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	/* USB host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	pxa_set_ohci_info(&pcm990_ohci_platform_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	pxa_set_i2c_info(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	pxa_set_ac97_info(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	printk(KERN_INFO "PCM-990 Evaluation baseboard initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }