Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * arch/arm/mach-pxa/include/mach/pcm027.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * (c) 2003 Phytec Messtechnik GmbH <armlinux@phytec.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * (c) 2007 Juergen Beisert <j.beisert@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  * Definitions of CPU card resources only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <mach/irqs.h> /* PXA_GPIO_TO_IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* phyCORE-PXA270 (PCM027) Interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PCM027_IRQ(x)          (IRQ_BOARD_START + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PCM027_BTDET_IRQ       PCM027_IRQ(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PCM027_FF_RI_IRQ       PCM027_IRQ(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PCM027_MMCDET_IRQ      PCM027_IRQ(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PCM027_PM_5V_IRQ       PCM027_IRQ(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PCM027_NR_IRQS		(IRQ_BOARD_START + 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* I2C RTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PCM027_RTC_IRQ_GPIO	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PCM027_RTC_IRQ		PXA_GPIO_TO_IRQ(PCM027_RTC_IRQ_GPIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PCM027_RTC_IRQ_EDGE	IRQ_TYPE_EDGE_FALLING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ADR_PCM027_RTC		0x51	/* I2C address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* I2C EEPROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ADR_PCM027_EEPROM	0x54	/* I2C address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Ethernet chip (SMSC91C111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PCM027_ETH_IRQ_GPIO	52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PCM027_ETH_IRQ		PXA_GPIO_TO_IRQ(PCM027_ETH_IRQ_GPIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PCM027_ETH_IRQ_EDGE	IRQ_TYPE_EDGE_RISING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PCM027_ETH_PHYS		PXA_CS5_PHYS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PCM027_ETH_SIZE		(1*1024*1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* CAN controller SJA1000 (unsupported yet) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PCM027_CAN_IRQ_GPIO	114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PCM027_CAN_IRQ		PXA_GPIO_TO_IRQ(PCM027_CAN_IRQ_GPIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PCM027_CAN_IRQ_EDGE	IRQ_TYPE_EDGE_FALLING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PCM027_CAN_PHYS		0x22000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PCM027_CAN_SIZE		0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* SPI GPIO expander (unsupported yet) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PCM027_EGPIO_IRQ_GPIO	27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PCM027_EGPIO_IRQ	PXA_GPIO_TO_IRQ(PCM027_EGPIO_IRQ_GPIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PCM027_EGPIO_IRQ_EDGE	IRQ_TYPE_EDGE_FALLING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PCM027_EGPIO_CS		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)  * TODO: Switch this pin from dedicated usage to GPIO if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)  * more than the MAX7301 device is connected to this SPI bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PCM027_EGPIO_CS_MODE	GPIO24_SFRM_MD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Flash memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PCM027_FLASH_PHYS	0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PCM027_FLASH_SIZE	0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* onboard LEDs connected to GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PCM027_LED_CPU		90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PCM027_LED_HEARD_BEAT	91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)  * This CPU module needs a baseboard to work. After basic initializing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)  * its own devices, it calls baseboard's init function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)  * TODO: Add your own basebaord init function and call it from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)  * inside pcm027_init(). This example here is for the developmen board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)  * Refer pcm990-baseboard.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) extern void pcm990_baseboard_init(void);