^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/mach-pxa/mfp-pxa2xx.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * PXA2xx pin mux configuration support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * The GPIOs on PXA2xx can be configured as one of many alternate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * functions, this is by concept samilar to the MFP configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * on PXA3xx, what's more important, the low power pin state and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * wakeup detection are also supported by the same framework.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gpio-pxa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <mach/pxa2xx-regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "mfp-pxa2xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "generic.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PGSR(x) __REG2(0x40F00020, (x) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define __GAFR(u, x) __REG2((u) ? 0x40E00058 : 0x40E00054, (x) << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define GAFR_L(x) __GAFR(0, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define GAFR_U(x) __GAFR(1, x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define GPLR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define GPDR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x0c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define GPSR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define GPCR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PWER_WE35 (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct gpio_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned valid : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned can_wakeup : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned keypad_gpio : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) unsigned dir_inverted : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) unsigned int mask; /* bit mask in PWER or PKWR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned int mux_mask; /* bit mask of muxed gpio bits, 0 if no mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned long config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static struct gpio_desc gpio_desc[MFP_PIN_GPIO127 + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static unsigned long gpdr_lpm[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static int __mfp_config_gpio(unsigned gpio, unsigned long c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned long gafr, mask = GPIO_bit(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int bank = gpio_to_bank(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) int uorl = !!(gpio & 0x10); /* GAFRx_U or GAFRx_L ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) int shft = (gpio & 0xf) << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) int fn = MFP_AF(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int is_out = (c & MFP_DIR_OUT) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (fn > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* alternate function and direction at run-time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) gafr = (uorl == 0) ? GAFR_L(bank) : GAFR_U(bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) gafr = (gafr & ~(0x3 << shft)) | (fn << shft);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (uorl == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) GAFR_L(bank) = gafr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) GAFR_U(bank) = gafr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (is_out ^ gpio_desc[gpio].dir_inverted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) GPDR(gpio) |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) GPDR(gpio) &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* alternate function and direction at low power mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) switch (c & MFP_LPM_STATE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) case MFP_LPM_DRIVE_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) PGSR(bank) |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) is_out = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) case MFP_LPM_DRIVE_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) PGSR(bank) &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) is_out = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) case MFP_LPM_INPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) case MFP_LPM_DEFAULT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* warning and fall through, treat as MFP_LPM_DEFAULT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) pr_warn("%s: GPIO%d: unsupported low power mode\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) __func__, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (is_out ^ gpio_desc[gpio].dir_inverted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) gpdr_lpm[bank] |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) gpdr_lpm[bank] &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* give early warning if MFP_LPM_CAN_WAKEUP is set on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * configurations of those pins not able to wakeup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if ((c & MFP_LPM_CAN_WAKEUP) && !gpio_desc[gpio].can_wakeup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) pr_warn("%s: GPIO%d unable to wakeup\n", __func__, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if ((c & MFP_LPM_CAN_WAKEUP) && is_out) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) pr_warn("%s: output GPIO%d unable to wakeup\n", __func__, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static inline int __mfp_validate(int mfp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int gpio = mfp_to_gpio(mfp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if ((mfp > MFP_PIN_GPIO127) || !gpio_desc[gpio].valid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) pr_warn("%s: GPIO%d is invalid pin\n", __func__, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) void pxa2xx_mfp_config(unsigned long *mfp_cfgs, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned long *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int i, gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) for (i = 0, c = mfp_cfgs; i < num; i++, c++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) gpio = __mfp_validate(MFP_PIN(*c));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (gpio < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) gpio_desc[gpio].config = *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) __mfp_config_gpio(gpio, *c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) void pxa2xx_mfp_set_lpm(int mfp, unsigned long lpm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned long flags, c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) gpio = __mfp_validate(mfp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (gpio < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) c = gpio_desc[gpio].config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) c = (c & ~MFP_LPM_STATE_MASK) | lpm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) __mfp_config_gpio(gpio, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) int gpio_set_wake(unsigned int gpio, unsigned int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct gpio_desc *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned long c, mux_taken;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (gpio > mfp_to_gpio(MFP_PIN_GPIO127))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) d = &gpio_desc[gpio];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) c = d->config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (!d->valid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* Allow keypad GPIOs to wakeup system when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * configured as generic GPIOs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (d->keypad_gpio && (MFP_AF(d->config) == 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) (d->config & MFP_LPM_CAN_WAKEUP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) PKWR |= d->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PKWR &= ~d->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) mux_taken = (PWER & d->mux_mask) & (~d->mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (on && mux_taken)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (d->can_wakeup && (c & MFP_LPM_CAN_WAKEUP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) PWER = (PWER & ~d->mux_mask) | d->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (c & MFP_LPM_EDGE_RISE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) PRER |= d->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) PRER &= ~d->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (c & MFP_LPM_EDGE_FALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) PFER |= d->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) PFER &= ~d->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PWER &= ~d->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PRER &= ~d->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PFER &= ~d->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #ifdef CONFIG_PXA25x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static void __init pxa25x_mfp_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* running before pxa_gpio_probe() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #ifdef CONFIG_CPU_PXA26x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) pxa_last_gpio = 89;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) pxa_last_gpio = 84;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) for (i = 0; i <= pxa_last_gpio; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) gpio_desc[i].valid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) for (i = 0; i <= 15; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) gpio_desc[i].can_wakeup = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) gpio_desc[i].mask = GPIO_bit(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* PXA26x has additional 4 GPIOs (86/87/88/89) which has the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * direction bit inverted in GPDR2. See PXA26x DM 4.1.1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) for (i = 86; i <= pxa_last_gpio; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) gpio_desc[i].dir_inverted = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static inline void pxa25x_mfp_init(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #endif /* CONFIG_PXA25x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #ifdef CONFIG_PXA27x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int pxa27x_pkwr_gpio[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 13, 16, 17, 34, 36, 37, 38, 39, 90, 91, 93, 94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 95, 96, 97, 98, 99, 100, 101, 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) int keypad_set_wake(unsigned int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) unsigned int i, gpio, mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct gpio_desc *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) for (i = 0; i < ARRAY_SIZE(pxa27x_pkwr_gpio); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) gpio = pxa27x_pkwr_gpio[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) d = &gpio_desc[gpio];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* skip if configured as generic GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (MFP_AF(d->config) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (d->config & MFP_LPM_CAN_WAKEUP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) mask |= gpio_desc[gpio].mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) PKWR |= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) PKWR &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define PWER_WEMUX2_GPIO38 (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define PWER_WEMUX2_GPIO53 (2 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define PWER_WEMUX2_GPIO40 (3 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define PWER_WEMUX2_GPIO36 (4 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define PWER_WEMUX2_MASK (7 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define PWER_WEMUX3_GPIO31 (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define PWER_WEMUX3_GPIO113 (2 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define PWER_WEMUX3_MASK (3 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define INIT_GPIO_DESC_MUXED(mux, gpio) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) gpio_desc[(gpio)].can_wakeup = 1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) gpio_desc[(gpio)].mask = PWER_ ## mux ## _GPIO ##gpio; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) gpio_desc[(gpio)].mux_mask = PWER_ ## mux ## _MASK; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static void __init pxa27x_mfp_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) int i, gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) pxa_last_gpio = 120; /* running before pxa_gpio_probe() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) for (i = 0; i <= pxa_last_gpio; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* skip GPIO2, 5, 6, 7, 8, they are not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * valid pins allow configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (i == 2 || i == 5 || i == 6 || i == 7 || i == 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) gpio_desc[i].valid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* Keypad GPIOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) for (i = 0; i < ARRAY_SIZE(pxa27x_pkwr_gpio); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) gpio = pxa27x_pkwr_gpio[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) gpio_desc[gpio].can_wakeup = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) gpio_desc[gpio].keypad_gpio = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) gpio_desc[gpio].mask = 1 << i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* Overwrite GPIO13 as a PWER wakeup source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) for (i = 0; i <= 15; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* skip GPIO2, 5, 6, 7, 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (GPIO_bit(i) & 0x1e4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) gpio_desc[i].can_wakeup = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) gpio_desc[i].mask = GPIO_bit(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) gpio_desc[35].can_wakeup = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) gpio_desc[35].mask = PWER_WE35;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) INIT_GPIO_DESC_MUXED(WEMUX3, 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) INIT_GPIO_DESC_MUXED(WEMUX3, 113);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) INIT_GPIO_DESC_MUXED(WEMUX2, 38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) INIT_GPIO_DESC_MUXED(WEMUX2, 53);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) INIT_GPIO_DESC_MUXED(WEMUX2, 40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) INIT_GPIO_DESC_MUXED(WEMUX2, 36);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static inline void pxa27x_mfp_init(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #endif /* CONFIG_PXA27x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static unsigned long saved_gafr[2][4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static unsigned long saved_gpdr[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static unsigned long saved_gplr[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static unsigned long saved_pgsr[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static int pxa2xx_mfp_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* set corresponding PGSR bit of those marked MFP_LPM_KEEP_OUTPUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) for (i = 0; i < pxa_last_gpio; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if ((gpio_desc[i].config & MFP_LPM_KEEP_OUTPUT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) (GPDR(i) & GPIO_bit(i))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (GPLR(i) & GPIO_bit(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) PGSR(gpio_to_bank(i)) |= GPIO_bit(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) PGSR(gpio_to_bank(i)) &= ~GPIO_bit(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) saved_gafr[0][i] = GAFR_L(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) saved_gafr[1][i] = GAFR_U(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) saved_gpdr[i] = GPDR(i * 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) saved_gplr[i] = GPLR(i * 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) saved_pgsr[i] = PGSR(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) GPSR(i * 32) = PGSR(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) GPCR(i * 32) = ~PGSR(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* set GPDR bits taking into account MFP_LPM_KEEP_OUTPUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) for (i = 0; i < pxa_last_gpio; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if ((gpdr_lpm[gpio_to_bank(i)] & GPIO_bit(i)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ((gpio_desc[i].config & MFP_LPM_KEEP_OUTPUT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) (saved_gpdr[gpio_to_bank(i)] & GPIO_bit(i))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) GPDR(i) |= GPIO_bit(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) GPDR(i) &= ~GPIO_bit(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static void pxa2xx_mfp_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) GAFR_L(i) = saved_gafr[0][i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) GAFR_U(i) = saved_gafr[1][i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) GPSR(i * 32) = saved_gplr[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) GPCR(i * 32) = ~saved_gplr[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) GPDR(i * 32) = saved_gpdr[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) PGSR(i) = saved_pgsr[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) PSSR = PSSR_RDH | PSSR_PH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define pxa2xx_mfp_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define pxa2xx_mfp_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct syscore_ops pxa2xx_mfp_syscore_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .suspend = pxa2xx_mfp_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .resume = pxa2xx_mfp_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static int __init pxa2xx_mfp_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (!cpu_is_pxa2xx())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (cpu_is_pxa25x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) pxa25x_mfp_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (cpu_is_pxa27x())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) pxa27x_mfp_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* clear RDH bit to enable GPIO receivers after reset/sleep exit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) PSSR = PSSR_RDH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* initialize gafr_run[], pgsr_lpm[] from existing values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) gpdr_lpm[i] = GPDR(i * 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) postcore_initcall(pxa2xx_mfp_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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