^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/mach-pxa/mainstone.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Support for the Intel HCDDBBVA0 Development Platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * (go figure how they came up with such name...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Nicolas Pitre
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Created: Nov 05, 2002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright: MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gpio/gpio-reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/gpio/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/mtd/partitions.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/input.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/gpio_keys.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/pwm_backlight.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/smc91x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/platform_data/i2c-pxa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/leds.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <asm/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <asm/memory.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <asm/mach/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <asm/mach/flash.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include "pxa27x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <mach/mainstone.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <mach/audio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <linux/platform_data/video-pxafb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <linux/platform_data/mmc-pxamci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <linux/platform_data/irda-pxaficp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <linux/platform_data/usb-ohci-pxa27x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <linux/platform_data/keypad-pxa27x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <mach/smemc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include "generic.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include "devices.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static unsigned long mainstone_pin_config[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Chip Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) GPIO15_nCS_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* LCD - 16bpp Active TFT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) GPIOxx_LCD_TFT_16BPP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) GPIO16_PWM0_OUT, /* Backlight */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* MMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) GPIO32_MMC_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) GPIO112_MMC_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) GPIO92_MMC_DAT_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) GPIO109_MMC_DAT_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) GPIO110_MMC_DAT_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) GPIO111_MMC_DAT_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* USB Host Port 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) GPIO88_USBH1_PWR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) GPIO89_USBH1_PEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* PC Card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) GPIO48_nPOE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) GPIO49_nPWE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) GPIO50_nPIOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) GPIO51_nPIOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) GPIO85_nPCE_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) GPIO54_nPCE_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) GPIO79_PSKTSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) GPIO55_nPREG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) GPIO56_nPWAIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) GPIO57_nIOIS16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* AC97 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) GPIO28_AC97_BITCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) GPIO29_AC97_SDATA_IN_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) GPIO30_AC97_SDATA_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) GPIO31_AC97_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) GPIO45_AC97_SYSCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* Keypad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) GPIO93_KP_DKIN_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) GPIO94_KP_DKIN_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) GPIO95_KP_DKIN_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) GPIO100_KP_MKIN_0 | WAKEUP_ON_LEVEL_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) GPIO101_KP_MKIN_1 | WAKEUP_ON_LEVEL_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) GPIO102_KP_MKIN_2 | WAKEUP_ON_LEVEL_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) GPIO97_KP_MKIN_3 | WAKEUP_ON_LEVEL_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) GPIO98_KP_MKIN_4 | WAKEUP_ON_LEVEL_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) GPIO99_KP_MKIN_5 | WAKEUP_ON_LEVEL_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) GPIO103_KP_MKOUT_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) GPIO104_KP_MKOUT_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) GPIO105_KP_MKOUT_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) GPIO106_KP_MKOUT_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) GPIO107_KP_MKOUT_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) GPIO108_KP_MKOUT_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) GPIO96_KP_MKOUT_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) GPIO117_I2C_SCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) GPIO118_I2C_SDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static struct resource smc91x_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .start = (MST_ETH_PHYS + 0x300),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .end = (MST_ETH_PHYS + 0xfffff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .start = MAINSTONE_IRQ(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .end = MAINSTONE_IRQ(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static struct smc91x_platdata mainstone_smc91x_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .flags = SMC91X_USE_8BIT | SMC91X_USE_16BIT | SMC91X_USE_32BIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) SMC91X_NOWAIT | SMC91X_USE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .pxa_u16_align4 = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static struct platform_device smc91x_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .name = "smc91x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .num_resources = ARRAY_SIZE(smc91x_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .resource = smc91x_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .platform_data = &mainstone_smc91x_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static int mst_audio_startup(struct snd_pcm_substream *substream, void *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) MST_MSCWR2 &= ~MST_MSCWR2_AC97_SPKROFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static void mst_audio_shutdown(struct snd_pcm_substream *substream, void *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) MST_MSCWR2 |= MST_MSCWR2_AC97_SPKROFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static long mst_audio_suspend_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static void mst_audio_suspend(void *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) mst_audio_suspend_mask = MST_MSCWR2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) MST_MSCWR2 |= MST_MSCWR2_AC97_SPKROFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static void mst_audio_resume(void *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) MST_MSCWR2 &= mst_audio_suspend_mask | ~MST_MSCWR2_AC97_SPKROFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static pxa2xx_audio_ops_t mst_audio_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .startup = mst_audio_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .shutdown = mst_audio_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .suspend = mst_audio_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .resume = mst_audio_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static struct resource flash_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .start = PXA_CS0_PHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .end = PXA_CS0_PHYS + SZ_64M - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .start = PXA_CS1_PHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .end = PXA_CS1_PHYS + SZ_64M - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static struct mtd_partition mainstoneflash0_partitions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .name = "Bootloader",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .size = 0x00040000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .mask_flags = MTD_WRITEABLE /* force read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .name = "Kernel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .size = 0x00400000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .offset = 0x00040000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) },{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .name = "Filesystem",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .size = MTDPART_SIZ_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .offset = 0x00440000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static struct flash_platform_data mst_flash_data[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .map_name = "cfi_probe",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .parts = mainstoneflash0_partitions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .nr_parts = ARRAY_SIZE(mainstoneflash0_partitions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .map_name = "cfi_probe",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .parts = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .nr_parts = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static struct platform_device mst_flash_device[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .name = "pxa2xx-flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .platform_data = &mst_flash_data[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .resource = &flash_resources[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .num_resources = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .name = "pxa2xx-flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .platform_data = &mst_flash_data[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .resource = &flash_resources[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .num_resources = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static struct pwm_lookup mainstone_pwm_lookup[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) PWM_LOOKUP("pxa27x-pwm.0", 0, "pwm-backlight.0", NULL, 78770,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) PWM_POLARITY_NORMAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static struct platform_pwm_backlight_data mainstone_backlight_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .max_brightness = 1023,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .dft_brightness = 1023,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static struct platform_device mainstone_backlight_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .name = "pwm-backlight",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .parent = &pxa27x_device_pwm0.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .platform_data = &mainstone_backlight_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static void __init mainstone_backlight_register(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) pwm_add_table(mainstone_pwm_lookup, ARRAY_SIZE(mainstone_pwm_lookup));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) ret = platform_device_register(&mainstone_backlight_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) printk(KERN_ERR "mainstone: failed to register backlight device: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) pwm_remove_table(mainstone_pwm_lookup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) ARRAY_SIZE(mainstone_pwm_lookup));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define mainstone_backlight_register() do { } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static struct pxafb_mode_info toshiba_ltm04c380k_mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .pixclock = 50000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .xres = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .yres = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .bpp = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .hsync_len = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .left_margin = 0x9f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .right_margin = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .vsync_len = 44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .upper_margin = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .lower_margin = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .sync = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static struct pxafb_mode_info toshiba_ltm035a776c_mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .pixclock = 110000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .xres = 240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .yres = 320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .bpp = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .hsync_len = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .left_margin = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .right_margin = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .vsync_len = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .upper_margin = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .lower_margin = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .sync = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static struct pxafb_mach_info mainstone_pxafb_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .num_modes = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static int mainstone_mci_init(struct device *dev, irq_handler_t mstone_detect_int, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* make sure SD/Memory Stick multiplexer's signals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * are routed to MMC controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) MST_MSCWR1 &= ~MST_MSCWR1_MS_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) err = request_irq(MAINSTONE_MMC_IRQ, mstone_detect_int, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) "MMC card detect", data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) printk(KERN_ERR "mainstone_mci_init: MMC/SD: can't request MMC card detect IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int mainstone_mci_setpower(struct device *dev, unsigned int vdd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct pxamci_platform_data* p_d = dev->platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (( 1 << vdd) & p_d->ocr_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) printk(KERN_DEBUG "%s: on\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) MST_MSCWR1 |= MST_MSCWR1_MMC_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) MST_MSCWR1 &= ~MST_MSCWR1_MS_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) printk(KERN_DEBUG "%s: off\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) MST_MSCWR1 &= ~MST_MSCWR1_MMC_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static void mainstone_mci_exit(struct device *dev, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) free_irq(MAINSTONE_MMC_IRQ, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static struct pxamci_platform_data mainstone_mci_platform_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .init = mainstone_mci_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .setpower = mainstone_mci_setpower,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .exit = mainstone_mci_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static void mainstone_irda_transceiver_mode(struct device *dev, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (mode & IR_SIRMODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) MST_MSCWR1 &= ~MST_MSCWR1_IRDA_FIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) } else if (mode & IR_FIRMODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) MST_MSCWR1 |= MST_MSCWR1_IRDA_FIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) pxa2xx_transceiver_mode(dev, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (mode & IR_OFF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) MST_MSCWR1 = (MST_MSCWR1 & ~MST_MSCWR1_IRDA_MASK) | MST_MSCWR1_IRDA_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) MST_MSCWR1 = (MST_MSCWR1 & ~MST_MSCWR1_IRDA_MASK) | MST_MSCWR1_IRDA_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static struct pxaficp_platform_data mainstone_ficp_platform_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .gpio_pwdown = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .transceiver_cap = IR_SIRMODE | IR_FIRMODE | IR_OFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .transceiver_mode = mainstone_irda_transceiver_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static struct gpio_keys_button gpio_keys_button[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .desc = "wakeup",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .code = KEY_SUSPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .type = EV_KEY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .gpio = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .wakeup = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static struct gpio_keys_platform_data mainstone_gpio_keys = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .buttons = gpio_keys_button,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .nbuttons = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static struct platform_device mst_gpio_keys_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .name = "gpio-keys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .platform_data = &mainstone_gpio_keys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static struct resource mst_cplds_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .start = MST_FPGA_PHYS + 0xc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .end = MST_FPGA_PHYS + 0xe0 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .start = PXA_GPIO_TO_IRQ(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .end = PXA_GPIO_TO_IRQ(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .start = MAINSTONE_IRQ(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .end = MAINSTONE_IRQ(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static struct platform_device mst_cplds_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .name = "pxa_cplds_irqs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .id = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .resource = &mst_cplds_resources[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .num_resources = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static struct platform_device *platform_devices[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) &smc91x_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) &mst_flash_device[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) &mst_flash_device[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) &mst_gpio_keys_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) &mst_cplds_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static struct pxaohci_platform_data mainstone_ohci_platform_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .port_mode = PMM_PERPORT_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .flags = ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static const unsigned int mainstone_matrix_keys[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) KEY(0, 0, KEY_A), KEY(1, 0, KEY_B), KEY(2, 0, KEY_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) KEY(3, 0, KEY_D), KEY(4, 0, KEY_E), KEY(5, 0, KEY_F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) KEY(0, 1, KEY_G), KEY(1, 1, KEY_H), KEY(2, 1, KEY_I),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) KEY(3, 1, KEY_J), KEY(4, 1, KEY_K), KEY(5, 1, KEY_L),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) KEY(0, 2, KEY_M), KEY(1, 2, KEY_N), KEY(2, 2, KEY_O),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) KEY(3, 2, KEY_P), KEY(4, 2, KEY_Q), KEY(5, 2, KEY_R),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) KEY(0, 3, KEY_S), KEY(1, 3, KEY_T), KEY(2, 3, KEY_U),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) KEY(3, 3, KEY_V), KEY(4, 3, KEY_W), KEY(5, 3, KEY_X),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) KEY(2, 4, KEY_Y), KEY(3, 4, KEY_Z),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) KEY(0, 4, KEY_DOT), /* . */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) KEY(1, 4, KEY_CLOSE), /* @ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) KEY(4, 4, KEY_SLASH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) KEY(5, 4, KEY_BACKSLASH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) KEY(0, 5, KEY_HOME),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) KEY(1, 5, KEY_LEFTSHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) KEY(2, 5, KEY_SPACE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) KEY(3, 5, KEY_SPACE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) KEY(4, 5, KEY_ENTER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) KEY(5, 5, KEY_BACKSPACE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) KEY(0, 6, KEY_UP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) KEY(1, 6, KEY_DOWN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) KEY(2, 6, KEY_LEFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) KEY(3, 6, KEY_RIGHT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) KEY(4, 6, KEY_SELECT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static struct matrix_keymap_data mainstone_matrix_keymap_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .keymap = mainstone_matrix_keys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .keymap_size = ARRAY_SIZE(mainstone_matrix_keys),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct pxa27x_keypad_platform_data mainstone_keypad_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .matrix_key_rows = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .matrix_key_cols = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .matrix_keymap_data = &mainstone_matrix_keymap_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .enable_rotary0 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .rotary0_up_key = KEY_UP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .rotary0_down_key = KEY_DOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .debounce_interval = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static void __init mainstone_init_keypad(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) pxa_set_keypad_info(&mainstone_keypad_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static inline void mainstone_init_keypad(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static int mst_pcmcia0_irqs[11] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) [0 ... 10] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) [5] = MAINSTONE_S0_CD_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) [8] = MAINSTONE_S0_STSCHG_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) [10] = MAINSTONE_S0_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static int mst_pcmcia1_irqs[11] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) [0 ... 10] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) [5] = MAINSTONE_S1_CD_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) [8] = MAINSTONE_S1_STSCHG_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) [10] = MAINSTONE_S1_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static struct gpiod_lookup_table mainstone_pcmcia_gpio_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .dev_id = "pxa2xx-pcmcia",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) GPIO_LOOKUP("mst-pcmcia0", 0, "a0vpp", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) GPIO_LOOKUP("mst-pcmcia0", 1, "a1vpp", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) GPIO_LOOKUP("mst-pcmcia0", 2, "a0vcc", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) GPIO_LOOKUP("mst-pcmcia0", 3, "a1vcc", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) GPIO_LOOKUP("mst-pcmcia0", 4, "areset", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) GPIO_LOOKUP("mst-pcmcia0", 5, "adetect", GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) GPIO_LOOKUP("mst-pcmcia0", 6, "avs1", GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) GPIO_LOOKUP("mst-pcmcia0", 7, "avs2", GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) GPIO_LOOKUP("mst-pcmcia0", 8, "abvd1", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) GPIO_LOOKUP("mst-pcmcia0", 9, "abvd2", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) GPIO_LOOKUP("mst-pcmcia0", 10, "aready", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) GPIO_LOOKUP("mst-pcmcia1", 0, "b0vpp", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) GPIO_LOOKUP("mst-pcmcia1", 1, "b1vpp", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) GPIO_LOOKUP("mst-pcmcia1", 2, "b0vcc", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) GPIO_LOOKUP("mst-pcmcia1", 3, "b1vcc", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) GPIO_LOOKUP("mst-pcmcia1", 4, "breset", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) GPIO_LOOKUP("mst-pcmcia1", 5, "bdetect", GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) GPIO_LOOKUP("mst-pcmcia1", 6, "bvs1", GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) GPIO_LOOKUP("mst-pcmcia1", 7, "bvs2", GPIO_ACTIVE_LOW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) GPIO_LOOKUP("mst-pcmcia1", 8, "bbvd1", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) GPIO_LOOKUP("mst-pcmcia1", 9, "bbvd2", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) GPIO_LOOKUP("mst-pcmcia1", 10, "bready", GPIO_ACTIVE_HIGH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static void __init mainstone_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) int SW7 = 0; /* FIXME: get from SCR (Mst doc section 3.2.1.1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) pxa2xx_mfp_config(ARRAY_AND_SIZE(mainstone_pin_config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* Register board control register(s) as GPIOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) gpio_reg_init(NULL, (void __iomem *)&MST_PCMCIA0, -1, 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) "mst-pcmcia0", MST_PCMCIA_INPUTS, 0, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) NULL, mst_pcmcia0_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) gpio_reg_init(NULL, (void __iomem *)&MST_PCMCIA1, -1, 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) "mst-pcmcia1", MST_PCMCIA_INPUTS, 0, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) NULL, mst_pcmcia1_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) gpiod_add_lookup_table(&mainstone_pcmcia_gpio_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) pxa_set_ffuart_info(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) pxa_set_btuart_info(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) pxa_set_stuart_info(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) mst_flash_data[0].width = (__raw_readl(BOOT_DEF) & 1) ? 2 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) mst_flash_data[1].width = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /* Compensate for SW7 which swaps the flash banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) mst_flash_data[SW7].name = "processor-flash";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) mst_flash_data[SW7 ^ 1].name = "mainboard-flash";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) printk(KERN_NOTICE "Mainstone configured to boot from %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) mst_flash_data[0].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* system bus arbiter setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * - Core_Park
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * - LCD_wt:DMA_wt:CORE_Wt = 2:3:4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) ARB_CNTRL = ARB_CORE_PARK | 0x234;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /* reading Mainstone's "Virtual Configuration Register"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) might be handy to select LCD type here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) mainstone_pxafb_info.modes = &toshiba_ltm04c380k_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) mainstone_pxafb_info.modes = &toshiba_ltm035a776c_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) pxa_set_fb_info(NULL, &mainstone_pxafb_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) mainstone_backlight_register();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) pxa_set_mci_info(&mainstone_mci_platform_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) pxa_set_ficp_info(&mainstone_ficp_platform_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) pxa_set_ohci_info(&mainstone_ohci_platform_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) pxa_set_i2c_info(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) pxa_set_ac97_info(&mst_audio_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) mainstone_init_keypad();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static struct map_desc mainstone_io_desc[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) { /* CPLD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .virtual = MST_FPGA_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .pfn = __phys_to_pfn(MST_FPGA_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .length = 0x00100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .type = MT_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) static void __init mainstone_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) pxa27x_map_io();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) iotable_init(mainstone_io_desc, ARRAY_SIZE(mainstone_io_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) /* for use I SRAM as framebuffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) PSLR |= 0xF04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) PCFR = 0x66;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * Driver for the 8 discrete LEDs available for general use:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * Note: bits [15-8] are used to enable/blank the 8 7 segment hex displays
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * so be sure to not monkey with them here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) struct mainstone_led {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) struct led_classdev cdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) u8 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * The triggers lines up below will only be used if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * LED triggers are compiled in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) const char *trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) } mainstone_leds[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) { "mainstone:D28", "default-on", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) { "mainstone:D27", "cpu0", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) { "mainstone:D26", "heartbeat" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) { "mainstone:D25", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) { "mainstone:D24", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) { "mainstone:D23", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) { "mainstone:D22", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) { "mainstone:D21", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static void mainstone_led_set(struct led_classdev *cdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) enum led_brightness b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) struct mainstone_led *led = container_of(cdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) struct mainstone_led, cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) u32 reg = MST_LEDCTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (b != LED_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) reg |= led->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) reg &= ~led->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) MST_LEDCTRL = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static enum led_brightness mainstone_led_get(struct led_classdev *cdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) struct mainstone_led *led = container_of(cdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) struct mainstone_led, cdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) u32 reg = MST_LEDCTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return (reg & led->mask) ? LED_FULL : LED_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static int __init mainstone_leds_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (!machine_is_mainstone())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* All ON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) MST_LEDCTRL |= 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) for (i = 0; i < ARRAY_SIZE(mainstone_leds); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) struct mainstone_led *led;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) led = kzalloc(sizeof(*led), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (!led)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) led->cdev.name = mainstone_leds[i].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) led->cdev.brightness_set = mainstone_led_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) led->cdev.brightness_get = mainstone_led_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) led->cdev.default_trigger = mainstone_leds[i].trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) led->mask = BIT(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (led_classdev_register(NULL, &led->cdev) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) kfree(led);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * Since we may have triggers on any subsystem, defer registration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * until after subsystem_init.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) fs_initcall(mainstone_leds_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /* Maintainer: MontaVista Software Inc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .atag_offset = 0x100, /* BLOB boot parameter setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .map_io = mainstone_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .nr_irqs = MAINSTONE_NR_IRQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .init_irq = pxa27x_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .handle_irq = pxa27x_handle_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .init_time = pxa_timer_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .init_machine = mainstone_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .restart = pxa_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) MACHINE_END
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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