Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * arch/arm/mach-pxa/include/mach/lpd270.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Author:	Lennert Buytenhek
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Created:	Feb 10, 2006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #ifndef __ASM_ARCH_LPD270_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __ASM_ARCH_LPD270_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define LPD270_CPLD_PHYS	PXA_CS2_PHYS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define LPD270_CPLD_VIRT	IOMEM(0xf0000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define LPD270_CPLD_SIZE	0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define LPD270_ETH_PHYS		(PXA_CS2_PHYS + 0x01000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* CPLD registers  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define LPD270_CPLD_REG(x)	(LPD270_CPLD_VIRT + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define LPD270_CONTROL		LPD270_CPLD_REG(0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define LPD270_PERIPHERAL0	LPD270_CPLD_REG(0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define LPD270_PERIPHERAL1	LPD270_CPLD_REG(0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define LPD270_CPLD_REVISION	LPD270_CPLD_REG(0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define LPD270_EEPROM_SPI_ITF	LPD270_CPLD_REG(0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define LPD270_MODE_PINS	LPD270_CPLD_REG(0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define LPD270_EGPIO		LPD270_CPLD_REG(0x30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define LPD270_INT_MASK		LPD270_CPLD_REG(0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define LPD270_INT_STATUS	LPD270_CPLD_REG(0x50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define LPD270_INT_AC97		(1 << 4)  /* AC'97 CODEC IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LPD270_INT_ETHERNET	(1 << 3)  /* Ethernet controller IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define LPD270_INT_USBC		(1 << 2)  /* USB client cable detection IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define LPD270_IRQ(x)		(IRQ_BOARD_START + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define LPD270_USBC_IRQ		LPD270_IRQ(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LPD270_ETHERNET_IRQ	LPD270_IRQ(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define LPD270_AC97_IRQ		LPD270_IRQ(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define LPD270_NR_IRQS		(IRQ_BOARD_START + 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #endif