^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/arch/arm/mach-pxa/lpd270.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Support for the LogicPD PXA270 Card Engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Derived from the mainstone code, which carries these notices:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Nicolas Pitre
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Created: Nov 05, 2002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright: MontaVista Software Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/fb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mtd/mtd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mtd/partitions.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pwm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/pwm_backlight.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/smc91x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/memory.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/mach-types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <asm/mach/arch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <asm/mach/map.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <asm/mach/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <asm/mach/flash.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include "pxa27x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include "lpd270.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <mach/audio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/platform_data/video-pxafb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/platform_data/mmc-pxamci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/platform_data/irda-pxaficp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <linux/platform_data/usb-ohci-pxa27x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <mach/smemc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include "generic.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include "devices.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static unsigned long lpd270_pin_config[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* Chip Selects */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) GPIO15_nCS_1, /* Mainboard Flash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) GPIO78_nCS_2, /* CPLD + Ethernet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* LCD - 16bpp Active TFT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) GPIO58_LCD_LDD_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) GPIO59_LCD_LDD_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) GPIO60_LCD_LDD_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) GPIO61_LCD_LDD_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) GPIO62_LCD_LDD_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) GPIO63_LCD_LDD_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) GPIO64_LCD_LDD_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) GPIO65_LCD_LDD_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) GPIO66_LCD_LDD_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) GPIO67_LCD_LDD_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) GPIO68_LCD_LDD_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) GPIO69_LCD_LDD_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) GPIO70_LCD_LDD_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) GPIO71_LCD_LDD_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) GPIO72_LCD_LDD_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) GPIO73_LCD_LDD_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) GPIO74_LCD_FCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) GPIO75_LCD_LCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) GPIO76_LCD_PCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) GPIO77_LCD_BIAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) GPIO16_PWM0_OUT, /* Backlight */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* USB Host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) GPIO88_USBH1_PWR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) GPIO89_USBH1_PEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* AC97 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) GPIO28_AC97_BITCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) GPIO29_AC97_SDATA_IN_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) GPIO30_AC97_SDATA_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) GPIO31_AC97_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) GPIO45_AC97_SYSCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static unsigned int lpd270_irq_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static void lpd270_mask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) int lpd270_irq = d->irq - LPD270_IRQ(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) __raw_writew(~(1 << lpd270_irq), LPD270_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) lpd270_irq_enabled &= ~(1 << lpd270_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static void lpd270_unmask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int lpd270_irq = d->irq - LPD270_IRQ(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) lpd270_irq_enabled |= 1 << lpd270_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static struct irq_chip lpd270_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .name = "CPLD",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .irq_ack = lpd270_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .irq_mask = lpd270_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .irq_unmask = lpd270_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static void lpd270_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned long pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) pending = __raw_readw(LPD270_INT_STATUS) & lpd270_irq_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* clear useless edge notification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) desc->irq_data.chip->irq_ack(&desc->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (likely(pending)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) irq = LPD270_IRQ(0) + __ffs(pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) generic_handle_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) pending = __raw_readw(LPD270_INT_STATUS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) lpd270_irq_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) } while (pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static void __init lpd270_init_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) pxa27x_init_irq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) __raw_writew(0, LPD270_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) __raw_writew(0, LPD270_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* setup extra LogicPD PXA270 irqs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) irq_set_chip_and_handler(irq, &lpd270_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) irq_set_chained_handler(PXA_GPIO_TO_IRQ(0), lpd270_irq_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) irq_set_irq_type(PXA_GPIO_TO_IRQ(0), IRQ_TYPE_EDGE_FALLING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static void lpd270_irq_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) __raw_writew(lpd270_irq_enabled, LPD270_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static struct syscore_ops lpd270_irq_syscore_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .resume = lpd270_irq_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int __init lpd270_irq_device_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (machine_is_logicpd_pxa270()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) register_syscore_ops(&lpd270_irq_syscore_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) device_initcall(lpd270_irq_device_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static struct resource smc91x_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .start = LPD270_ETH_PHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .end = (LPD270_ETH_PHYS + 0xfffff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .start = LPD270_ETHERNET_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .end = LPD270_ETHERNET_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct smc91x_platdata smc91x_platdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static struct platform_device smc91x_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .name = "smc91x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .num_resources = ARRAY_SIZE(smc91x_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .resource = smc91x_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .dev.platform_data = &smc91x_platdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static struct resource lpd270_flash_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .start = PXA_CS0_PHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .end = PXA_CS0_PHYS + SZ_64M - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .start = PXA_CS1_PHYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .end = PXA_CS1_PHYS + SZ_64M - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static struct mtd_partition lpd270_flash0_partitions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .name = "Bootloader",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .size = 0x00040000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .mask_flags = MTD_WRITEABLE /* force read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .name = "Kernel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .size = 0x00400000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .offset = 0x00040000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .name = "Filesystem",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .size = MTDPART_SIZ_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .offset = 0x00440000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static struct flash_platform_data lpd270_flash_data[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .name = "processor-flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .map_name = "cfi_probe",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .parts = lpd270_flash0_partitions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .nr_parts = ARRAY_SIZE(lpd270_flash0_partitions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .name = "mainboard-flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .map_name = "cfi_probe",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .parts = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .nr_parts = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static struct platform_device lpd270_flash_device[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .name = "pxa2xx-flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .platform_data = &lpd270_flash_data[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .resource = &lpd270_flash_resources[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .num_resources = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .name = "pxa2xx-flash",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .platform_data = &lpd270_flash_data[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .resource = &lpd270_flash_resources[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .num_resources = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static struct pwm_lookup lpd270_pwm_lookup[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) PWM_LOOKUP("pxa27x-pwm.0", 0, "pwm-backlight.0", NULL, 78770,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) PWM_POLARITY_NORMAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static struct platform_pwm_backlight_data lpd270_backlight_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .max_brightness = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .dft_brightness = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static struct platform_device lpd270_backlight_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .name = "pwm-backlight",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .parent = &pxa27x_device_pwm0.dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .platform_data = &lpd270_backlight_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* 5.7" TFT QVGA (LoLo display number 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static struct pxafb_mode_info sharp_lq057q3dc02_mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .pixclock = 150000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .xres = 320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .yres = 240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .bpp = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .hsync_len = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .left_margin = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .right_margin = 0x0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .vsync_len = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .upper_margin = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .lower_margin = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static struct pxafb_mach_info sharp_lq057q3dc02 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .modes = &sharp_lq057q3dc02_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .num_modes = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) LCD_ALTERNATE_MAPPING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* 12.1" TFT SVGA (LoLo display number 2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static struct pxafb_mode_info sharp_lq121s1dg31_mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .pixclock = 50000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .xres = 800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .yres = 600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .bpp = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .hsync_len = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .left_margin = 0x52,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .right_margin = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .vsync_len = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .upper_margin = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .lower_margin = 0x0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static struct pxafb_mach_info sharp_lq121s1dg31 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .modes = &sharp_lq121s1dg31_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .num_modes = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) LCD_ALTERNATE_MAPPING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* 3.6" TFT QVGA (LoLo display number 3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static struct pxafb_mode_info sharp_lq036q1da01_mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .pixclock = 150000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .xres = 320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .yres = 240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .bpp = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .hsync_len = 0x0e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .left_margin = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .right_margin = 0x0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .vsync_len = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .upper_margin = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .lower_margin = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static struct pxafb_mach_info sharp_lq036q1da01 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .modes = &sharp_lq036q1da01_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .num_modes = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) LCD_ALTERNATE_MAPPING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* 6.4" TFT VGA (LoLo display number 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static struct pxafb_mode_info sharp_lq64d343_mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .pixclock = 25000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .xres = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .yres = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .bpp = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .hsync_len = 0x31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .left_margin = 0x89,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .right_margin = 0x19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .vsync_len = 0x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .upper_margin = 0x22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .lower_margin = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static struct pxafb_mach_info sharp_lq64d343 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .modes = &sharp_lq64d343_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .num_modes = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) LCD_ALTERNATE_MAPPING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* 10.4" TFT VGA (LoLo display number 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static struct pxafb_mode_info sharp_lq10d368_mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .pixclock = 25000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .xres = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .yres = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .bpp = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .hsync_len = 0x31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .left_margin = 0x89,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .right_margin = 0x19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .vsync_len = 0x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .upper_margin = 0x22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .lower_margin = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static struct pxafb_mach_info sharp_lq10d368 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .modes = &sharp_lq10d368_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .num_modes = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) LCD_ALTERNATE_MAPPING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* 3.5" TFT QVGA (LoLo display number 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static struct pxafb_mode_info sharp_lq035q7db02_20_mode = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .pixclock = 150000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .xres = 240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .yres = 320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .bpp = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .hsync_len = 0x0e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .left_margin = 0x0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .right_margin = 0x0a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .vsync_len = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .upper_margin = 0x05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .lower_margin = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static struct pxafb_mach_info sharp_lq035q7db02_20 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .modes = &sharp_lq035q7db02_20_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .num_modes = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) LCD_ALTERNATE_MAPPING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static struct pxafb_mach_info *lpd270_lcd_to_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static int __init lpd270_set_lcd(char *str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (!strncasecmp(str, "lq057q3dc02", 11)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) lpd270_lcd_to_use = &sharp_lq057q3dc02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) } else if (!strncasecmp(str, "lq121s1dg31", 11)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) lpd270_lcd_to_use = &sharp_lq121s1dg31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) } else if (!strncasecmp(str, "lq036q1da01", 11)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) lpd270_lcd_to_use = &sharp_lq036q1da01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) } else if (!strncasecmp(str, "lq64d343", 8)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) lpd270_lcd_to_use = &sharp_lq64d343;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) } else if (!strncasecmp(str, "lq10d368", 8)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) lpd270_lcd_to_use = &sharp_lq10d368;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) } else if (!strncasecmp(str, "lq035q7db02-20", 14)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) lpd270_lcd_to_use = &sharp_lq035q7db02_20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) printk(KERN_INFO "lpd270: unknown lcd panel [%s]\n", str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) __setup("lcd=", lpd270_set_lcd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static struct platform_device *platform_devices[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) &smc91x_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) &lpd270_backlight_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) &lpd270_flash_device[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) &lpd270_flash_device[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static struct pxaohci_platform_data lpd270_ohci_platform_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .port_mode = PMM_PERPORT_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .flags = ENABLE_PORT_ALL | POWER_CONTROL_LOW | POWER_SENSE_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static void __init lpd270_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) pxa2xx_mfp_config(ARRAY_AND_SIZE(lpd270_pin_config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) pxa_set_ffuart_info(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) pxa_set_btuart_info(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) pxa_set_stuart_info(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) lpd270_flash_data[0].width = (__raw_readl(BOOT_DEF) & 1) ? 2 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) lpd270_flash_data[1].width = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * System bus arbiter setting:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * - Core_Park
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * - LCD_wt:DMA_wt:CORE_Wt = 2:3:4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ARB_CNTRL = ARB_CORE_PARK | 0x234;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) pwm_add_table(lpd270_pwm_lookup, ARRAY_SIZE(lpd270_pwm_lookup));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) pxa_set_ac97_info(NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (lpd270_lcd_to_use != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) pxa_set_fb_info(NULL, lpd270_lcd_to_use);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) pxa_set_ohci_info(&lpd270_ohci_platform_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static struct map_desc lpd270_io_desc[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .virtual = (unsigned long)LPD270_CPLD_VIRT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .pfn = __phys_to_pfn(LPD270_CPLD_PHYS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .length = LPD270_CPLD_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .type = MT_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static void __init lpd270_map_io(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) pxa27x_map_io();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) iotable_init(lpd270_io_desc, ARRAY_SIZE(lpd270_io_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* for use I SRAM as framebuffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) PSLR |= 0x00000F04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) PCFR = 0x00000066;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* Maintainer: Peter Barada */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .atag_offset = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .map_io = lpd270_map_io,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .nr_irqs = LPD270_NR_IRQS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .init_irq = lpd270_init_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .handle_irq = pxa27x_handle_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .init_time = pxa_timer_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .init_machine = lpd270_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .restart = pxa_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) MACHINE_END
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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